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ST20C2 数据表(PDF) 73 Page - STMicroelectronics |
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ST20C2 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 212 page  diss 73/212 ® diss disable skip Code: 23 F0 Description: Disable a ‘skip’ guard in an alternative sequence. Areg is the offset from the byte following the altend to the start of the guarded process and Breg is the boolean guard. If this is the first ready guard then the value in Areg is stored in workspace and Areg is set to true, otherwise Areg is set to false. Note that this instruction should be used as part of an alternative sequence following an altwt or taltwt instruction. Definition: if (Breg = false)– boolean guard is false Areg ′← false else if (word[Wptr @ pw.Temp] = NoneSelected.o) Areg ′← false – this is the first ready guard else – another guard was selected { word ′[Wptr @ pw.Temp] ← Areg Areg ′← true } Breg ′← Creg Creg ′← undefined Error signals: none Comments: Secondary instruction. Uses the pw.Temp slot in the process workspace. See also: alt altend altwt enbs talt taltwt |
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