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ST20C2 数据表(PDF) 160 Page - STMicroelectronics |
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ST20C2 数据表(HTML) 160 Page - STMicroelectronics |
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160 / 212 page  shl ® 160/212 shl shift left Code: 24 F1 Description: Logical shift left Breg by Areg places, filling with z ero bits. If the initial Areg is not between 0 and 31 inclusive then the result is zero. The result is only defined for shift lengths less than the word length. Definition: if (0 ≤ Areg < BitsPerWord) Areg ′← Breg << Areg else Areg ′← undefined Breg ′← Creg Creg ′← undefined Error signals: none Comments: Secondar y instruction. The behavior for shift lengths outside the stated range is implementation dependent. See also: lshl lshr norm shr |
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