ST7263B datasheet(117/132 Pages) STMICROELECTRONICS

117 / 132 page

ST7263B

117/132

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

13.10.2 SCI - Serial Communications Interface

Subject to general operating condition for VDD,

fCPU, and TA unless otherwise specified.

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(RDI and TDO).

13.10.3 I2C - Inter IC Control Interface

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SDAI and SCLI).

The ST7 I2C interface meets the requirements of

the Standard I2C communication protocol de-

scribed in the following table.

(Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified)

Notes:

1. Data based on standard I2C protocol requirement, not tested in production.

2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL.

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of

SCL signal.

Symbol

Parameter

Conditions

Standard

Baud

Rate

Unit

fCPU

Accuracy

vs. Standard

Prescaler

fTx

fRx

Communication frequency

8MHz

~0.16%

Conventional Mode

TR (or RR)=128, PR=13

TR (or RR)= 32, PR=13

TR (or RR)= 16, PR=13

TR (or RR)= 8, PR=13

TR (or RR)= 4, PR=13

TR (or RR)= 16, PR= 3

TR (or RR)= 2, PR=13

TR (or RR)= 1, PR=13

300

1200

2400

4800

9600

10400

19200

38400

~300.48

~1201.92

~2403.84

~4807.69

~9615.38

~10416.67

~19230.77

~38461.54

Symbol

Parameter

Standard mode I2C

Fast mode I2C

Unit

Min 1)

Max 1)

Min 1)

Max 1)

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

0 3)

0 2)

900 3)

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

20+0.1Cb

300

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

20+0.1Cb

300

th(STA)

START condition hold time

4.0

0.6

µs

tsu(STA)

Repeated START condition setup time

4.7

0.6

tsu(STO)

STOP condition setup time

4.0

0.6

tw(STO:STA) STOP to START condition time (bus free)

4.7

1.3

Capacitive load for each bus line

400

ST7263B 数据表(PDF) 117 Page - STMicroelectronics

ST7263B 数据表(HTML) 117 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载