ST75C540 datasheet(66/84 Pages) STMICROELECTRONICS

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These flowcharts show two CPU variables labeled

IBUF and Tx_Completed, they are necessary for

the understanding of the mechanism, but there is

different manners to implement it. These two vari-

ables have the following meanning :

- IBUF : Thisis the numberof the DUALRAM Buffer

currently in use by the Host processor. It starts

with 0 and then alternate 1, 0, 1, 0, ...

- Tx_Completed : This is a Flag to dialog with the

interrupt process in order to stop properly the

transmition.

The other Buffers are sent under interrupt control

(refer to the interrupt flow chart, Figure 30).

To stop properly the transmition, without loss of

Data (see Figure 31).

XI - TRANSMITTING DATA IN PARALLEL MODE (continued)

RETURN

EXECUTE_IT_TRANSMIT

Yes

Tx_COMPLETED ?

Yes

IBUF = 1

WRITE AA, 55, ...

INTO DTTBF1

WRITE 08 INTO DTTBS1

IBUF = 0

WRITE AA, 55, ...

INTO DTTBF0

WRITE 08 INTO DTTBS0

IBUF = 1

(1)

Figure 30

XMIT 00

STOP

Tx_COMPLETED = TRUE

Yes

STA_106 = 1

Stop sending parallel

data (delayed)

Stop signal

Semaphore with interrupt

Wait until last buffer is

transmitted and CCITT

stop sequence completed

Figure 31

XI.4 - Error Detection

Error occurs when the ST75C530/540 need some

bitsfrom the transmitbuffer DTTBSx and this buffer

is empty. This condition is called “Underflow”.

This error is signaled in the bit ERR_TX of the

SYSERR byte, and generates an interrupt IT0.To

clear the error a CSE 01 command must be issued.

An Underflow contition occurs when :

- In synchronous mode: the host processor “for-

gets” to feed the current DTTBSx buffer.

- In HDLC mode: when, while inside a frame, the

host processor “forgets” to feed the current

DTTBSx buffer. An abort frame is transmitted in

place of the regular Buffer.

- This condition cannot append in UART mode.

When an underflow condition occur the host must

restart the whole parallel initialization, as explained

above.

XI.5 - Synchronous Mode

XI.5.1 - Description

In synchronousmode the ST75C530/540transmits

the bits contained in the DUAL RAM Buffer without

any modification. It starts with the Bit 0 of the

DTTBF0[0] byte.

XI.5.2 - Status Word Format

The Transmit Status Bytes DTTBS0 or DTTBS1

have the same following meaning(see table below).

DTTBSx in Synchronous Mode

Field

Pos. Value

Definition

BUFF_LENG 3 .. 0

Other

Buffer empty.

1 Byte to transmit

(DTTBFx[0]).

2 Bytes to transmit

(DTTBFx[0] and

DTTBFx[1]).

8 Bytes to transmit

(

DTTBFx[0 .. 7]).

Not allowed.

Other

7 .. 4

Reserved, must be 0.

This status byte must be written by the Host, after

filing the corresponding data buffer DTTBFx[0..7]

with the right number of data bytes to transmit.

This status byte is cleared by the ST75C530/540,

just before generating the IT2 interrupt.

ST75C530 - ST75C540

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