ST75C540 datasheet(21/84 Pages) STMICROELECTRONICS

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VI - USER INTERFACE

VI.1 - Dual Port Ram Description

The dual port RAM is the standard interface be-

tween the host controller and the ST75C530/540,

for either commands or data. This memory is ad-

dressed through a 7-bit address bus. The locations

from $00 to $3F are RAM location, while locations

from $40 to $60 are control registers dedicated to

the interrupt handling and the general IO port and

Relay output.

Severalfunctionalareas are defined in the dual port

RAM mapping :

- the command area,

- the report area,

- the status area,

- the optional status area,

- the data buffer area,

- the interrupt control area,

- the general I/O and Relay Output area.

VI.1.1 - Mapping

VI.1.1.1 - Command Area

The command area is located from $00 to $04.

Address $00 holds the command byte COMSYS,

and the next four locations hold the parameters

COMPAR[0..3].The command parameters must be

entered before the command word is issued. Once

the command has been entered,the command byte

is reset and an acknowledge report is issued. Anew

command should not be issued before the acknow-

ledge counter COMACK is incremented.

VI.1.1.2 - Report Area

The report area is located from address $05 to

address $07. Location $05 holds the acknowledge

counter COMACK. Each time a command is ac-

knowledged, the report bytes COMREP[0..1] (if

any) are written by the ST75C530/540 into loca-

tions $06 and $07, and the content of COMACK is

in c r eme n t e d. T h i s

c ount er al l o w s

t he

ST75C530/540 to accurately monitor the com-

mand processing.

VI.1.1.3 - Status Area

The statusarea is located from address$08 to $0B.

The errorstatusword SYSERR is locatedat address

$08. This error status word is updated each time an

error condition occurs. An optional interruption IT0

may additionallybe triggered in the case of an error

condition. Locations $09 and $0A hold the general

status bytes STATUS[0..1]. The meaning of the bits

dependson the mode of operation,and is described

in Chapter VIII. The third byte at address $0B holds

the Quality Monitor byte STAQUA.

VI.1.1.4 - Optional Status Area

The user can program (through the DOSR com-

mand) the four locations STAOPT[0..3] of the Op-

tional Status Area ($0C to $0F) for the real time

monitoring of four arbitrary memory locations.

VI.1.1.5 - Data Buffer Area

The data area is made of four 8-byte buffers

(see Paragraph VI.1.3 “Host Interface Summary”).

Two are dedicated to transmission and the two

others to reception. Each of the four buffers is

attached to a status byte. the meaningof the status

byte depends on the selected format of transmis-

sion. Within each buffer, D0 represents the first bit

in time.

VI.1.1.6 - VOCODER Buffer Area

(VOCODER Mode)

This area is made of a 18+2 byte buffer. This buffer

contains the VOCODER frame. The first 18 bytes

VOCDATA contain the coded frame and the other

2 bytes VOCCORR the Error corrections bit (only

valid in low bit rate mode).

In the Receive Mode (CODER) the ST75C530/540

codes the received samples and writes the corres-

ponding bytes in the buffer. If the low bit rate mode

is selected, the ST75C530/540computes the Error

corrections 2 bytes and writes them in the buffer.

In th e Tr an sm it M od e ( DE CO D ER ) th e

ST75C530/540reads the 18 coded bytes decodes

them and sends the signal to the analog output. In

the low bit rate mode if the Error Correction is

enabled, prior the decoding, the ST75C530/540

reads the 2 Error Correction Bytes and, if any,

corrects the first 18 bytes.

A mechanism of flags to share the buffer access

between the ST75C530/540and the hostcontroller

is controlled by the VOCSTA byte :

- In CODER mode, when the ST75C530/540 has

finis-hed writing the VOCDATA and VOCCORR

bytes, it writes $14 in VOCSTA and generate an

Interrupt IT1. The host must read the Data buffer

then clear the VOCSTA byte.

- In DECODER mode, the host must feed the

VOCDATA and, optionaly,the VOCCORR bytes,

then write $14 (if low bit rate) or $12 (if ADPCM)

in VOCSTA. The ST75C530/540 will read the

VOCDATA and VOCCORR bytes, clear the

VOCSTA and generate an Interrupt IT1. A si-

lence frame can be generated, in either low bit

rate or ADPCM mode, by writing 00 in all the

VOCDATA buffer, including the Error Correction

Bytes VOCCORR.

ST75C530 - ST75C540

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