ST75C540 datasheet(71/84 Pages) STMICROELECTRONICS

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Establish the reception (see Figure 39).

XII - RECEIVING IN PARALLEL MODE (continued)

CONF 0F 08 00 01

SYNC1

Yes

STA_109 = 1

FORM 00 (opt)

Select V.29 9600bps

Arm V.29 receiver

Wait until V.29

carrier detected

Format synchronous

Clear the first

buffers #0 and #1

In case of lost of carrier

while in data mode

CLEAR FIRST BUFFER

WRITE 00 INTO DTRBFS0

WRITE 00 INTO DTRBFS1

SELECT NEXT BUFFER

IBUF = 0

ENABLE IT3

ITMASK = 0 x 88

RET

Subroutine :

CLEAR FIRST BUFFER

Yes

STA_109 = 0

Figure 39

Notes : 1. At that step the host can check that the corresponding

DTRBSx buffer is full (different from $00), otherwise it is

an error.

2. This means read BUFF_LENG bytes, inside the Receive

buffer

DTRBFx starting from location DTRBFx[0] to

DTRBFx[BUFF_LENG - 1]. In synchronous mode, the

BUFF_LENG isalways 8 bytes, except when a STA_109

lost appears in the middle of the buffer.

RETURN

Yes

IBUF = 1

READ DTRBS1

EXTRACT BUFF_LENG

IBUF = 0

EXECUTE_IT_RECEIVE

READ DTRBF1 DATA

BUFF_LENG TIMES (2)

WRITE 00 INTO DTRBS1

READ DTRBS0

EXTRACT BUFF_LENG

IBUF = 1

READ DTRBF0 DATA

BUFF_LENG TIMES (2)

WRITE 00 INTO DTRBS0

(1)

Figure 40

These flowcharts show one CPU variable labeled

IBUF which is necessary for the understanding of

the mechanism, but there are different manners to

implement it.

- IBUF : thisis the number of the DUAL RAM buffer

currently in use by the Host processor. It starts wit

0 an then alternates 1, 0, 1, 0, ...

The received bits are read by an interrupt routine

(See Figure 40).

XII.4 - Error Detection

Error occurs when the ST75C530/540 has re-

ceived some bits and that the buffer

DTRBSx is not

empty, this condition is called “Overflow”.

This error is signaled in the bit ERR_RX of the

SYSERR byte, and generates an interrupt IT0. To

clear the error a

CSE 02 command must be issued.

An Overflow condition occurs when :

- In synchronous mode: the host processor “for-

gets” to empty the current DTRBSx buffer.

- In HDLC mode: when, while inside a frame, the

host processors “forgets” to empty the current

DTRBSx buffer.

- In UART mode, this cannot happen.

When an Overflow condition occurs the host must

restart the whole parallel initialisation.

ST75C530 - ST75C540

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