ST75C540 datasheet(72/84 Pages) STMICROELECTRONICS

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XII - RECEIVING IN PARALLEL MODE (continued)

XII.5 - Synchronous Mode

XII.5.1 - Description

In synchronous mode the ST75C530/540 writes

the received bit into the DUAL RAM Buffer without

any modification. It starts with the Bit 0 of the

DTRBF0[0] byte.

XII.5.2 - Status Word Format

The receiveStatus Byte DTRBS0 or DTRBS1 have

the same following meaning (See Table below).

The BUFF_LENG is always 8 except when a lost

of carrier (STA_109 going to 0) happens.

This status byte is set by the ST75C530/540, just

before generating the IT3 interrupt.

XII.6 - HDLC Mode

XII.6.1 - Description

In HDLC mode the ST75C530/540 extracts from

the received HDLC frame the Data information

only. It reports, trough the DUAL Ram buffer, only

data information and frame validity. The mecha-

nism is as follows :

- As long as the ST75C530/540 receives continu-

ous HDLC Flag $7E, nothing happens. Note that

the ST75C530/540 allows zero sharing between

adjacent flags.

- When the ST75C530/540 receives some data, it

removes inserted “zero” if needed, and starts to

compute the CRC. As soon as its internal buffer

is full, the ST75C530/540writes the received data

i n to the DTRBFx b u ffer a nd se ts th e

BUFF_SFRM inside the DTRBSx status byte.

- Wh e n

r ec ei v i ng

addit i onal dat a, t h e

ST75C530/540 feeds the buffer just like in syn-

chronous mode.

- When the ST75C530/540 receives a closing flag

(which can be shared with the following opening

flag) it compares the received CRC with its inter-

nal computation. It writes the contents of the

received last data into the DTRBFx buffer, sets

the BUFF_EFRM bit and reports any frame error

in the

DTRBSx register via the BUFF_ERRS bits.

Reported errors are :

• CRC error (lowest priority): the received CRC

is not equal to the computed CRC. Some bits,

inside the frame, are erroneous.

• Non Byte-Aligned frame (middle priority): the

received data bit count (after deletion of the

“zero inserted”), between the opening and the

closing flag, is not a multiple of 8.

• Aborted frame (highest priority): the frame was

aborted with at least 7 consecutive “1”

- An abort frame can be also detected, while in the

inter frame mode, if instead of receiving $7E flag,

the ST75C530/540receive more than 7 consecu-

tive “1”. In this case only one Aborted frame is

signaled, event if the ”1” condition is maintained.

DTRBSx in Synchronous Mode

Field

Pos. Value

Definition

BUFF_LENG 3 .. 0

Other

Buffer empty.

1 Byte received

(

DTRBFx[0]).

2 Bytes received

(DTRBFx[0] and

DTRBFx[1]).

8 Bytes received

(

DTRBFx[0 .. 7]).

Not used.

Other

7 .. 4

Not used.

XII.6.2 - Status Word Format

DTRBSx in HDLC Mode

Field

Pos. Value

Definition

BUFF_LENG 3 .. 0

other

Buffer empty.

1 Byte received

(

DTRBFx[0]).

2 Bytes received

(

DTRBFx[0] and

DTRBFx[1]).

8 Bytes received

(DTRBFx[0 .. 7]).

Not allowed.

BUFF_ERRS 5 .. 4

0 0

No error.

CRC error.

Non Byte-Aligned frame.

Aborted frame.

BUFF_SFRM

Data stream.

Start of frame : the buffer

is a beginning of frame.

BUFF_EFRM

Data stream.

End of frame : the buffer

is a closing frame.

ST75C530 - ST75C540

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