ST75C540 datasheet(70/84 Pages) STMICROELECTRONICS

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XII - RECEIVING IN PARALLEL MODE

XII.1 - Description

When the STA_109 (CD) signal goes on, the

ST75C530/540 will write received data into the

DUAL RAM buffer DTRBS0 at first.

XII.1.1 - Initialization

The host processor must enable the IT3 receive

interrupt first.

Then it must empty the two DTRBS0 and DTRBS1

registers by writting $00 at these locations.

As soon as the first IT3 interrupt appears, the host

must proceed with the DTRBS0 buffer.

XII.1.2 - Loss of Carrier

Eac h t im e a lo ss of ca rr ier ap pe ars the

ST75C530/540 stops updating the Data buffer. If

the carrier reappers the host must proceed again

with the initialisation sequence.

XII.1.3 - FSK Synchronization

The FSK Full Duplex demodulator uses an algo-

rithm based on the transitions of the received sig-

nal. The synchronization mechanism is adjusted

with each signal transiton in order to sample the

demod ulated signal at the middle of the bit

(see Figure 37).

XII.2 - Modem Flow Chart

When in parallel data mode, each time the

ST75C530/540 has receive some bit of data it

executes the following routine (see Figure 38).

Where x start with the value 0 and toggle between

1 and 0.

DEMODULATED

SIGNAL

SAMPLE TIME

RECEIVE BIT

Figure 37

Yes

BEGIN

WRITE BIT IN

INTERNAL BUFFER

FULL

SELECT NEXT DUAL

RAM BUFFER X

Yes

DTRBSx = 0

MOVE DATA FROM INTERNAL

BUFFER TO DTRBFx

WRITE DTRBSx

RAISE IT3 INTERRUPT

RETURN

SIGNAL ERROR

INTO ERR_Rx

RAISE IT0 INTERRUPT

SELECT DUAL

RAM BUFFER x = 0

RETURN

Figure 38

XII.3 - Host Flow Chart

Hereafter are flowcharts to :

- Establish a V.29 reception.

- Receive synchronous data. This task is per-

formed under interrupt.

- Handle properly some temporary loss of carrier.

ST75C530 - ST75C540

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