ST75C540 datasheet(22/84 Pages) STMICROELECTRONICS

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VI.1.1.7 - Interrupt Control Area

The interrupt area, that start after the address $40

controls the behaviour of the Interrupts mecha-

nism. Register ITSRCR defines the source of the

interrupt, the register ITMASK allows independent

enabling or disabling of any of the interrupt’s

source, registers ITREST0 to ITREST6 reset the

corresponding interrupt source.

Theseregisters are not affectedby a INITcommand,

they are only reseted by a Hardware RESET signal.

VI.1.1.8 - General IO and Relay Output Area

A set of 5 registers is directly accessible by the

controller to program the General IO pins and

Relay Outputs (see Paragraph VI.1.3 “Host Inter-

face Summary”). Two registers IODIR0 and IO-

DIR1 define the type of the IO pin, either Input or

Output (0 = input, 1 = output), and two registers

IODATA0 and IODATA1 define the IO pin signals.

The fifth register defines the Relay output signals.

Theseregisters are not affectedby a INITcommand,

they are only reseted by a Hardware RESET signal.

The general IO are setup as input after the power

up or an hardware RESET. The relay output are

open after power up or an hardware RESET.

VI.1.2 - Interruptions

The ST75C530/540 can generate 7 interrupts for

the controller. The interrupt handling is made with

a set of registers located from $40 to $5F.

The interruptions generated by the ST75C530/540

com e f rom sev er al sour ces. Once the

ST75C530/540raises an interrupt, a signal (SINTR)

is sent to the controller. The controller has then to

processthe interruptandclear it. Theinterruptsource

can be examined in the interrupt source register

ITSRCR located a $50. According to the ITSRCR

bits, the interrupt source can be determined. Then

writing a zero at one of the memory location $40 to

$46 (Reset Interrupt Register ITRES[0..6]) will re-

set the corresponding interrupt (and thus acknow-

ledge it). The source of the interrupt can be masked

globally or individually using the Interrupt Mast

The interrupt sources are :

- IT0 : Error

This signifies that an error has occurred and the

error code is available in the error status byte

SYSERR. This byte can be selectively cleared by

the CSE command.

- IT1 : VOCODER Buffer

Each time the ST75C530/540 have coded a

frame (CODER Mode) or decoded a frame (DE-

CODER Mode) this interrupt is generated.

- IT2 : Tx Buffer

Each time the ST75530/C540frees a data buffer,

this interrupt is generated.

- IT3 : Rx Buffer

Each time the ST75C530/540 has filled a data

buffer, this interrupt is generated.

- IT4 : Status Byte

This signifies that the status byte has changed

and must be checked by the controller.

- IT5 : Low Power Mode

The ST75C530/540has been awakened from the

low power mode by a low level on the RING pin

or a dummy write issued by the host.

- IT6 : Command Acknowledge

This signifies that the ST75C530/540 has read

the last command entered by the host, incre-

mented the command counter COMACK, and is

ready for a new command.

Note : Interrupt registers are cleared after a Hard-

ware RESET. These registers are not affected by

a INIT Command.

VI - USER INTERFACE (continued)

ST75C530 - ST75C540

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