ST75C540 datasheet(76/84 Pages) STMICROELECTRONICS

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XIV - TRANSPARENT MODE DATA EXCHANGE

The mode uses the DPR locations to exchange

samples between the host and the AFE’s. To allow

maximum interrupt latency, the DSP uses internal

buffers to store samples and updates the DPR

buffers when internal buffers are ready. The DPR

buffers are bidirectional, thus doubling the effective

DPR capacity.

The transfer mechanism is depicted below :

1. At baud rate (every 4 samples at 9.6kHz), the

DSP transfers 4 samples from the Modem AFE

to the internal receive buffer, after sending them

through a high-passfilter with a transfer function

H(z) = (z-1)/ (z-0.875) used to remove all DC

components from the signal, and transfers

4 samplesfrom the Internal transmit bufferto the

Modem AFE. This comes from the currently

implemented internal scheduling. The same

operation is performed for the voice AFE.

2. After 3 bauds, the internal receive buffer is full

(the internal transmit buffer is also empty), the

DPR buffer is copied to the internal transmit

buffer, then the internal receive buffer is copied

into the DPR.

3. A host interrupt is generated : during servicing,

the host reads the DPR sample buffer then

writes it with new transmitted samples.

XIV.1 - Sample buffers

The mode uses the DPR locations to exchange

samples between the host and the AFE’s ; since no

data transfer (HDLC, UART) occurs in this mode,

the full 0x10 .. 0x3F DPR locations are available.

The Modem sample buffer (MODEMDPR) uses

locations 0x10 to 0x27 (24 bytes) to exchange

12 MAFE samples. The audio sample buffer

(AUDIODPR) uses locations 0x28 to 0x3F to ex-

change 12 VAFE samples. Samples are repre-

sented in 16-bit linear data format, byte order is

little-Endian (Intel-like, LSByte at low address),and

consecutive locations correspond to consecutive

samples in time. Example : locations (0x10, 0x11)

correspond to the first sample (LSB, MSB) re-

ceived from the line AFE.

XIV.2 - Interrupts

The DSP signal events to the host using the inter-

rupt mailbox (ITREST[0..6], ITMASK, ITSRCR).

IT2 is set by the DSP whenever the DPR buffers

are ready. This interrupt source can be masked

through ITMASK, and acknowledged using

ITSRCR[0..6]. The host interrupt service routine

should read received samples from the DPR, write

transmitted samples to the DPR, then acknow-

ledge by clearing the IT2 flag. The interrupt latency

is approximately equal to the interrupt period, i.e.

T = 1/800 = 1.25ms. Overrun and underrun condi-

tions may occur if the host interrupt latency ex-

ceeds the previous value. Since this situation is

unrecoverable, no specific action is taken. Never-

theless, for debug purposes the user can detect

this condition by probing the interrupt line (SINTR),

and trigger on a pulse width greater than the maxi-

mum allowed latency.

ST75C530 - ST75C540

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