ADE7569 datasheet(119/136 Pages) AD

119 / 136 page

Preliminary Technical Data

ADE7566/ADE7569

Rev. PrA | Page 119 of 136

SERIAL PERIPHERAL INTERFACE (SPI)

The ADE7566/ADE7569 integrate a complete hardware serial

peripheral interface on-chip. The SPI is full duplex so that 8 bits

of data are synchronously transmitted and simultaneously

received. This SPI implementation is double buffered, allowing

users to read the last byte of received data while a new byte is

shifted in. The next byte to be transmitted can be loaded while

the current byte is shifted out.

The SPI port can be configured for master or slave operation.

The physical interface to the SPI is via MISO (P0.5), MOSI (P0.4),

SCLK (P0.6), and SS (P0.7) pins, while the firmware interface is

via the SPI Configuration Register SFR (SPIMOD1, 0xE8), the

SPI Configuration Register SFR (SPIMOD2, 0xE9), the SPI

Interrupt Status Register SFR (SPISTAT, 0xEA), the SPI/I2C

Transmit Buffer SFR (SPI2CTx, 0x9A), and the SPI/I2C Receive

Buffer SFR (SPI2CRx, 0x9B).

Note that the SPI pins are shared with the I2C pins. Therefore, the

user can enable only one interface at a time. The SCPS bit in the

Configuration SFR (CFG, 0xAF) selects which peripheral is

active.

SPI SFR REGISTER LIST

Table 133. SPI SFR Register List

SFR Address

Name

R/W

Length

Default

Description

0x9A

SPI2CTx

SPI/I2C Data Out Register (see Table 134).

0x9B

SPI2CRx

SPI/I2C Data in Register (see Table 135).

0xE8

SPIMOD1

R/W

0x10

SPI Configuration Register (see Table 136).

0xE9

SPIMOD2

R/W

SPI Configuration Register. (see Table 137).

0xEA

SPISTAT

R/W

SPI/I2C Interrupt Status Register (see Table 138).

Table 134. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)

Bit No.

Mnemonic

Default

Description

7 to 0

SPI2CTx

SPI or I2C Transmit Buffer. When SPI2CTx SFR is written, its content is transferred to the transmit FIFO

input. When a write is requested, the FIFO output is sent on the SPI or I2C bus.

Table 135. SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B)

Bit No.

Mnemonic

Default

Description

7 to 0

SPI2CRx

SPI or I2C Receive Buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is transferred

to SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.

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