ADE7569 datasheet(120/136 Pages) AD

120 / 136 page

ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 120 of 136

Table 136. SPI Configuration Register SFR (SPIMOD1, 0xE8)

Bit No.

Address

Mnemonic

Default

Description

7 to 5

0xEF to 0xEE

Reserved

Reserved.

0xED

INTMOD

SPI Interrupt Mode.

INTMOD

Result

SPI interrupt set when SPI Rx buffer is full.

SPI interrupt set when SPI Tx buffer is empty.

0xEC

AUTO_SS

Master Mode, SS Output Control (see Figure 95).

AUTO_SS

Result

The SS is held low while this bit is cleared. This allows manual chip select

control using the SS pin.

Single Byte Read or Write. The SS goes low during a single byte transmission

and then returns high.

Continuous Transfer. The SS goes low during the duration of the multibyte

continuous transfer and then returns high.

0xEB

SS_EN

Slave Mode, SS Input Enable.

When this bit is set to Logic 1, the SS pin is defined as the slave select input pin for the

SPI slave interface.

0xEA

RxOFW

Receive Buffer Overflow Write Enable.

RxOFW

Result

If the SPI2CRx SFR has not been read when a new data byte is received,

the new byte is discarded.

If the SPI2CRx SFR has not been read when a new data byte is received,

the new byte overwrites the old data.

1 to 0

0xE9 to 0xE8

SPIR[1:0]

Master Mode, SPI SCLK Frequency.

SPIR[1:0]

Result

fCORE/8 = 512 kHz (if fCORE = 4.096 MHz)

fCORE/16 = 256 kHz (if fCORE = 4.096 MHz)

fCORE/32 = 128 kHz (if fCORE = 4.096 MHz)

fCORE/64 = 64 kHz (if fCORE = 4.096 MHz)

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