ADE7569 datasheet(125/136 Pages) AD

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Preliminary Technical Data

ADE7566/ADE7569

Rev. PrA | Page 125 of 136

I2C COMPATIBLE INTERFACE

The ADE7566/ADE7569 support a fully licensed I2C interface.

The I2C interface is implemented as a full hardware master.

SDATA is the data I/O pin, and SCLK is the serial clock. These

two pins are shared with the MOSI and SCLK pins of the on-chip

SPI interface. Therefore, the user can enable only one interface

or the other on these pins at any given time. The SCPS bit in the

Configuration SFR (CFG, 0xAF) selects which peripheral is

active.

The two pins used for data transfer, SDATA and SCLK, are

configured in a wire-AND format that allows arbitration in a

multimaster system.

The transfer sequence of a I2C system consists of a master device

initiating a transfer by generating a start condition while the bus

is idle. The master transmits the address of the slave device and

the direction of the data transfer in the initial address transfer. If

the slave acknowledges, the data transfer is initiated. This continues

until the master issues a stop condition and the bus becomes idle.

SERIAL CLOCK GENERATION

The I2C master in the system generates the serial clock for a

transfer. The master channel can be configured to operate in

fast mode (256 kHz) or standard mode (32 kHz).

The bit rate is defined in the I2CMOD SFR as follows:

]

[

CORE

SCLK

SLAVE ADDRESSES

The I2C Slave Address SFR (I2CADR, 0xE9) contains the slave

device ID. The LSB of this register contains a read/write request.

A write to this SFR starts the I2C communication.

I2C SFR REGISTER LIST

The I2C peripheral interface consists of five SFRs:

•

I2CMOD

•

SPI2CSTAT

•

I2CADR

•

SPI2CTx

•

SPI2CRx

Because the SPI and I2C serial interfaces share the same pins,

they also share the same SFRs, such as the SPI2CTx and SPIXCRx

SFRs. In addition, the I2CMOD, I2CADR, SPI2CSTAT, and

SPI2CTx SFRs are shared with the SPIMOD1, SPIMOD2, and

SPISTAT SFRs, respectively.

Table 140. I2C SFR Register List

SFR Address

Name

R/W

Length

Default

Description

0x9A

SPI2CTx

SPI/I2C Data out Register (see Table 134).

0x9B

SPI2CRx

SPI/I2C Data in Register (see Table 135).

0xE8

I2CMOD

R/W

I2C Configuration Register (see Table 141).

0xE9

I2CADR

R/W

I2C Configuration Register (see Table 142).

0xEA

SPI2CSTAT

R/W

SPI/I2C Interrupt Status Register (see Table 143).

Table 141. I2C Mode Register SFR (I2CMOD, 0xE8)

Bit No.

Address

Mnemonic

Default

Description

0xEF

I2CEN

I2C Enable Bit. When this bit is set to Logic 1, the I2C interface is enabled. A write to the

I2CADR SFR starts a communication.

6 to 5

0xEE to 0xED

I2CR[1:0]

I2C SCLK Frequency.

I2CR[1:0]

Result

fCORE/16 = 256 kHz if fCORE = 4.096 MHz

fCORE/32 = 128 kHz if fCORE = 4.096 MHz

fCORE/64 = 64 Hz if fCORE = 4.096 MHz

fCORE/128= 32 kHz if fCORE = 4.096 MHz

4 to 0

0xEC to 0xE8

I2CRCT[4:0]

Configures the length of the I2C received FIFO buffer. The I2C peripheral stops when

I2CRCT, Bit[4:0] + 1 byte have been read or if an error has occurred.

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