ADE7569 datasheet(129/136 Pages) AD

129 / 136 page

Preliminary Technical Data

ADE7566/ADE7569

Rev. PrA | Page 129 of 136

I/O PORTS

PARALLEL I/O

The ADE7566/ADE7569 use three input/output ports to

exchange data with external devices. In addition to performing

general-purpose I/O, some are capable of driving an LCD or

performing alternate functions for the peripherals available on-

chip. In general, when a peripheral is enabled, the pins

associated with it cannot be used as a general-purpose I/O. The

I/O port can be configured through the SFRs in Table 145.

Table 145. I/O Port SFRs

SFR

Address

Bit

Addressable

Description

0x80

Yes

Port 0 Register.

0x90

Yes

Port 1 Register.

0xA0

Yes

Port 2 Register.

EPCFG

0x9F

Extended Port

Configuration.

PINMAP0

0xB2

Port 0 Weak

Pull-Up Enable.

PINMAP1

0xB3

Port 1 Weak

Pull-Up Enable.

PINMAP2

0xB4

Port 2 Weak

Pull-Up Enable.

The three bidirectional I/O ports have internal pull-ups that can

be enabled or disabled individually for each pin. The internal

pull-ups are enabled by default. Disabling an internal pull-up

causes a pin to become open-drain. Weak internal pull-ups are

configured through the PINMAPx SFRs.

Figure 101 shows a typical bit latch and I/O buffer for an I/O

pin. The bit latch (one bit in the each port’s SFR) is represented

as a Type D flip-flop, which clocks in a value from the internal

bus in response to a write-to-latch signal from the CPU. The

Q output of the flip-flop is placed on the internal bus in response

to a read-latch signal from the CPU. The level of the port pin

itself is placed on the internal bus in response to a read pin

signal from the CPU. Some instructions that read a port activate

the read latch signal, and others activate the read pin signal. See

the Read-Modify-Write Instructions section for details.

READ

LATCH

INTERNAL

BUS

WRITE

TO LATCH

READ

LATCH

DVDD

Px.x

INTERNAL

PULL-UP

ALTERNATE

OUTPUT

FUNCTION

ALTERNATE

INPUT

FUNCTION

CLOSED: PINMAPx.x = 0

OPEN: PINMAPx.x = 1

Figure 101. Port 0 Bit Latch and I/O Buffer

Weak Internal Pull-Ups Enabled

A pin with weak internal pull-up enabled is used as an input by

writing a 1 to the pin. The pin is pulled high by the internal pull-

ups, and the pin is read using the circuitry shown in Figure 101.

If the pin is driven low externally, it sources current because of

the internal pull-ups.

A pin with internal pull-up enabled is used as an output by

writing a 1 or a 0 to the pin to control the level of the output. If

a 0 is written to the pin, it drives a logic low output voltage

(VOL) and is capable of sinking TBD mA.

Open Drain (Weak Internal Pull-Ups Disabled)

When the weak internal pull-up on a pin is disabled, the pin

becomes open-drain. Use this open-drain pin as a high impedance

input by writing a 1 to the pin. The pin is read using the circuitry

shown in Figure 101. The open drain option is preferable for

inputs because it draws less current than the internal pull-ups

that were enabled.

To use an open-drain pin as a general-purpose output, an external

pull-up resistor is required. Open drain outputs are convenient

for changing the voltage to a logic high. The ADE7566/ADE7569

are 3.3 V devices, so an external resistor pulled up to 5 V may

ease interfacing to a 5 V IC, although most 5 V ICs are tolerant

of 3.3 V inputs. Pins with 0s written to them drive a logic low

output voltage (VOL) and are capable of sinking 1.6 mA.

38 kHz Modulation

Every ADE7566/ADE7569 provides a 38 kHz modulation

signal. The 38 kHz modulation is accomplished by internally

XOR’ing the level written to the I/O pin with a 38 kHz square

wave. Then, when a 0 is written to the I/O pin, it is modulated

as shown in Figure 102.

38kHz MODULATION

SIGNAL

OUTPUT AT

MOD38 PIN

LEVEL WRITTEN

TO MOD38

Figure 102. 38 kHz Modulation

Uses for this 38 kHz modulation include IR modulation of

a UART transmit signal or a low power signal to drive an

LED. The modulation can be enabled or disabled with the

MOD38EN bit in the CFG SFR. The 38 kHz modulation is

available on 8 pins, selected by the MOD38[7:0] bits in the

Extended Port Configuration SFR (EPCFG, 0x9F).

ADE7569 数据表(PDF) 129 Page - Analog Devices

ADE7569 数据表(HTML) 129 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE7569 数据表(PDF) 129 Page - Analog Devices

ADE7569 数据表(HTML) 129 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载