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ADE7566 数据表(PDF) 40 Page - Analog Devices |
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ADE7566 数据表(HTML) 40 Page - Analog Devices |
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40 / 136 page  ADE7566/ADE7569 Preliminary Technical Data Rev. PrA | Page 40 of 136 Table 37. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD) Bit No. Interrupt Flag Description 7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not enabled by clearing Bit 2 of MODE1 register. 6 CF1 Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse output is not enabled by clearing Bit 1 of MODE1 register. 5 VAEOF Logic 1 indicates that the VAHR register has overflowed. 4 REOF1 Logic 1 indicates that the VARHR register has overflowed. 3 AEOF Logic 1 indicates that the WATTHR register has overflowed. 2 VAEHF Logic 1 indicates that the VAHR register is half-full. 1 REHF1 Logic 1 indicates that the VARHR register is half-full. 0 AEHF Logic 1 indicates that the WATTHR register is half-full. 1 This function is not available in the ADE7566 part. Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) Bit No. Interrupt Flag Description 7 RESET Indicates the end of a reset (for both software and hardware reset). 6 – Reserved. 5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). 4 PKI Logic 1 indicates that current channel has exceeded the IPKLVL value 3 PKV Logic 1 indicates that voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. 1 ZXTO Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles. 0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel. Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9) Bit No. Interrupt Enable Bit Description 7 to 5 Reserved Reserved. 4 VARSIGN1 When set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core. 3 APSIGN When set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core. 2 VANOLOAD When set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052 core. 1 RNOLOAD1 When set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052 core. 0 APNOLOAD When set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7566 part. Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA) Bit No. Interrupt Enable Bit Description 7 CF2 When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core. 6 CF1 When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core. 5 VAEOF When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core. 4 REOF1 When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core. 3 AEOF When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core. 2 VAEHF When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core. 1 REHF1 When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core. 0 AEHF When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7566 part. |
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