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ADE7566 数据表(PDF) 12 Page - Analog Devices |
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ADE7566 数据表(HTML) 12 Page - Analog Devices |
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12 / 136 page  ADE7566/ADE7569 Preliminary Technical Data Rev. PrA | Page 12 of 136 Table 5. SPI Master Mode Timing (SPICPHA = 0) Parameters Parameter Description Min Typ Max Unit tSL SCLK low pulse width (SPIR + 1) × tCORE1 ns tSH SCLK high pulse width (SPIR + 1) × tCORE1 ns tDAV Data output valid after SCLK edge 25 ns tDOSU Data output setup before SCLK edge 75 ns tDSU Data input setup time before SCLK edge TBD ns tDHD Data input hold time after SCLK edge TBD ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLK rise time 5 12.5 ns tSF SCLK fall time 5 12.5 ns 1 tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz. SCLK (SPICPOL = 0) t DSU SCLK (SPICPOL = 1) MOSI MISO MSB LSB LSB IN BITS 6–1 BITS 6–1 t DHD t DR t DAV t DF t DOSU t SH t SL t SR t SF MSB IN Figure 5. SPI Master Mode Timing (SPICPHA = 0) |
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