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ADE7566 数据表(PDF) 14 Page - Analog Devices |
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ADE7566 数据表(HTML) 14 Page - Analog Devices |
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14 / 136 page  ADE7566/ADE7569 Preliminary Technical Data Rev. PrA | Page 14 of 136 Table 7. SPI Slave Mode Timing (SPICPHA = 0) Parameters Parameter Description Min Typ Max Unit tSS SS to SCLK edge 0 ns tSL SCLK low pulse width (SPIR + 1) × tCORE1 ns tSH SCLK high pulse width (SPIR + 1) × tCORE1 ns tDAV Data output valid after SCLK edge 25 ns tDSU Data input setup time before SCLK edge TBD ns tDHD Data input hold time after SCLK edge TBD ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLK rise time 5 12.5 ns tSF SCLK fall time 5 12.5 ns tDOSS Data output valid after SS edge 25 ns tSFS SS high after SCLK edge 0 ns 1 tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz. MSB MOSI BITS 6–1 tDHD tDSU LSB IN BITS 6–1 LSB tDR tDF tDAV MISO tSR tSF tSFS tSS SCLK (SPICPOL = 1) SCLK (SPICPOL = 0) SS tSH tSL tDOSS MSB IN Figure 7. SPI Slave Mode Timing (SPICPHA= 0) |
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