ADE7566 datasheet(82/136 Pages) AD

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ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 82 of 136

INTERRUPT FLAGS

The interrupt flags and status flags associated with the interrupt vectors are shown in Table 68 and Table 69. Most of the interrupts have

flags associated with them.

Table 68. Interrupt Flags

Interrupt Source

Flags

Bit Address

Description

IE0

TCON.1

IE0

External Interrupt 0.

TF0

TCON.5

TF0

Timer 0.

IE1

TCON.3

IE1

External Interrupt 1.

TF1

TCON.7

TF1

Timer 1.

SCON.1

Transmit Interrupt.

RI + TI

SCON.0

Receive Interrupt.

T2CON.7

TF2

Timer 2 Overflow Flag.

TF2 + EXF2

T2CON.6

EXF2

Timer 2 External Flag.

ITEMP (Temperature ADC)

–

Temperature ADC Interrupt. Does not have an interrupt flag associated with it.

IPSM (Power Supply)

IPSMF.6

FPSM

PSM Interrupt Flag.

IADE (Energy Measurement DSP)

MIRQSTL.7

–

Read MIRQSTH, MIRQSTM, MIRQSTL.

Table 69. Status Flags

Interrupt Source

Flags

Bit Address

Description

ITEMP (Temperature ADC)

–

Temperature ADC Interrupt. Does not have a status flag associated with it.

SPI2CSTAT

–

SPI Interrupt Status Register.

ISPI/I2CI

SPI2CSTAT

–

I2C Interrupt Status Register.

TIMECON.7

–

RTC Midnight Flag.

IRTC (RTC Interval Timer)

TIMECON.2

–

RTC Alarm Flag.

WDT (Watchdog Timer)

WDCON.2

WDS

Watchdog Timeout Flag.

A functional block diagram of the interrupt system is shown in

Figure 75. Note that the PSM interrupt is the only interrupt in

the highest priority level.

If an external wake-up event occurs to wake the ADE7566

/ADE7569 from PSM2, a pending external interrupt is

generated. When the EX0 or EX1 bits in the Interrupt Enable

SFR (IE, 0xA8) are set to enable external interrupts, the

program counter is loaded with the IE0 or IE1 interrupt vector.

The IE0 and IE1 interrupt flags in the TCON register are not

affected by events that occur when the 8052 MCU core is shut

down during PSM2. See the Power Supply Monitor Interrupt

(PSM) section.

The RTC, temperature ADC, and I2C/SPI interrupts are latched

such that pending interrupts cannot be cleared without entering

their respective interrupt service routines. Clearing the RTC

midnight flags and alarm flags does not clear a pending RTC

interrupt. Similarly, clearing the I2C/SPI status bits in the SPI

Interrupt Status Register SFR (SPISTAT, 0xEA) does not cancel

a pending I2C/SPI interrupt. These interrupts remain pending

until the RTC or I2C/SPI interrupt vectors are enabled. Their

respective interrupt service routines are entered shortly

thereafter.

Figure 75 shows how the interrupts are cleared when the

interrupt service routines are entered. Some interrupts with

multiple interrupt sources are not automatically cleared;

specifically the PSM, ADE, UART, and Timer 2 interrupt

vectors. Note that the INT0 and INT1 interrupts are only

cleared if the external interrupt is configured to be triggered by

a falling edge by setting IT0 in the Timer/Counter 0 and

Timer/Counter 1 Control SFR (TCON, 0x88). If INT0 or INT1

is configured to interrupt on a low level, the interrupt service

routine is reentered until the respective pin goes high.

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