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ADE7566 数据表(PDF) 61 Page - Analog Devices |
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ADE7566 数据表(HTML) 61 Page - Analog Devices |
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61 / 136 page  Preliminary Technical Data ADE7566/ADE7569 Rev. PrA | Page 61 of 136 APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power. ∫ = dt t Power Apparent Energy Apparent ) ( (33) The ADE7566/ADE7569 achieve the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAHR[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 34 expresses the relationship. ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ × = ∑ ∞ = → 0 0 ) ( n T T nT wer ApparentPo Lim Energy Apparent (34) where: n is the discrete time sample number. T is the sample period. The discrete time sample period (T) for the accumulation register in the ADE7566/ADE7569 is 1.22 μs (5/MCLK). Figure 63 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy theoretically remains positive. The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register is 0, the internal apparent energy register is divided by 1. VADIV is an 8-bit unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAHR[23:0]). The RVAHR register (24 bits long) is provided to read the apparent energy. This register is reset to 0 after a read operation Note that the apparent energy register is unsigned. By setting the VAEHF and VAEOF bits in the Interrupt Enable Register 2 SFR (MIRQENM, 0xDA), the ADE7566/ADE7569 can be configured to issue an ADE interrupt to the 8052 core when the apparent energy register is half-full or when an overflow occurs. The half-full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register. Integration Times Under Steady Load As mentioned in the Apparent Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set to 0x000, the average word value from the apparent power stage is 0x1A36E2 (see the Apparent Power Calculation section). The maximum value that can be stored in the apparent energy register before it overflows is 224 or 0xFF,FFFF. The average word value is added to the internal register, which can store 248 or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows: Time = min 33 . 3 sec 199 s 22 . 1 0xD055 FFFF FFFF, 0xFFFF, = = μ × (35) When VADIV is set to a value different from 0, the integration time varies, as shown in Equation 36. Time = TimeWDIV = 0 × VADIV (36) VADIV APPARENT POWER or Irms + + VAHR[23:0] APPARENT POWER OR Irms IS ACCUMULATED (INTEGRATED) IN THE APPARENT ENERGY REGISTER 23 0 48 0 48 0 % TIME (nT) T APPARENT POWER SIGNAL = P Figure 63. Apparent Energy Calculation |
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