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ADE7566 数据表(PDF) 15 Page - Analog Devices |
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ADE7566 数据表(HTML) 15 Page - Analog Devices |
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15 / 136 page  Preliminary Technical Data ADE7566/ADE7569 Rev. PrA | Page 15 of 136 Table 8. UART Timing (Shift Register Mode) Parameters 4.096 MHz Core Clock Variable Core Clock Parameter Description Min Typ Max Min Typ Max Unit tXLXL Serial port clock cycle time 2.93 12 × tCORE1 μs tQVXH Output data setup to clock TBD μs tDVXH Input data setup to clock TBD μs tXHDX Input data hold after clock TBD μs tXHQX Output data hold after clock TBD μs 1 tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz. SET RI OR SET TI BIT 6 tXLXL TxD (OUTPUT CLOCK) RxD (OUTPUT DATA) RxD (INPUT DATA) BIT 1 LSB LSB BIT 1 BIT 6 MSB tXHQX tQVXH tDVXH tXHDX Figure 8. UART Timing in Shift Register Mode |
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