ADE7566 datasheet(126/136 Pages) AD

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ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 126 of 136

Table 142. I2C Slave Address SFR (I2CADR, 0xE9)

Bit No.

Mnemonic

Default

Description

7 to 1

I2CSLVADR

Address of the I2C Slave Being Addressed. Writing to this register starts the I2C transmission (read or write).

I2CR_W

Command Bit for Read or Write. When this bit is set to Logic 1, a read command is transmitted on the I2C

bus. Data from slave in the SPI2CRx SFR is expected after command byte. When this bit is set to Logic 0, a

write command is transmitted on the I2C bus. Data to slave is expected in the SPI2CTx SFR.

Table 143. I2C Interrupt Status Register SFR (SPI2CSTAT, 0xEA)

Bit No.

Mnemonic

Default

Description

I2CBUSY

This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied

I2CNOACK

I2C No Acknowledgement Transmit Interrupt. This bit is set to Logic 1 when the slave device

does not send an acknowledgement. The I2C communication is stopped after this event.

Write a 0 to this bit to clear it.

I2CRxIRQ

I2C Receive Interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.

Write a 0 to this bit to clear it.

I2CTxIRQ

I2C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.

Write a 0 to this bit to clear it.

3 to 2

I2CFIFOSTAT[1:0]

Status Bits for 3- or 4-Bytes Deep I2C FIFO. The FIFO monitored in these 2 bits is the one currently

used in I2C communication (receive or transmit) because only one FIFO is active at a time.

I2CFIFOSTAT[1:0]

Result

FIFO empty

Reserved

FIFO half full

FIFO full

I2CACC_ERR

Set when trying to write and read at the same time. Write a 0 to this bit to clear it.

I2CTxWR_ERR

Set when write was attempted when I2C transmit FIFO was full. Write a 0 to this bit to clear it.

READ AND WRITE OPERATIONS

Figure 98 and Figure 99 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select

whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated

automatically by the I2C peripheral. The master generated NACK before the end of a read operation is also automatically generated after

the I2CRCT, Bits[4:0] bits have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a

stop at the end of the read or write operation, the master generates a start condition and continues with the next communication.

Reading the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B)

Reading the SPI2CRx SFR should be done with a 2-cycle instruction, such as

Mov a, spi2crx or Mov R0, spi2crx.

A 3-cycle instruction such as

Mov 3dh, spi2crx

will not transfer the right data into RAM Address 0x3d.

SCLK

SDATA

START BY

MASTER

ACK BY

SLAVE

ACK BY

MASTER

FRAME 2

DATA BYTE 1 FROM MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

FRAME N + 1

DATA BYTE N FROM SLAVE

STOP BY

MASTER

NACK BY

MASTER

Figure 98. I2C Read Operation

SCLK

SDATA

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

FRAME 2

DATA BYTE 1 FROM MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

STOP BY

MASTER

R/W

Figure 99. I2C Write Operation

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