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T80C5112-RKFCL 数据表(PDF) 68 Page - ATMEL Corporation |
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T80C5112-RKFCL 数据表(HTML) 68 Page - ATMEL Corporation |
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68 / 97 page  68 Rev. B - November 10, 2000 Preliminary T80C5112 Reset Value = XXXX X00Xb No Bit addressable Table 43. IE1 Register IE1 (S:C0h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - - - ESPI EADC - Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 ESPI SPI Interrupt Enable bit Clear to disable the SPI interrupt. Set to enable the SPI interrupt. 1 EADC A/D Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. |
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