T80C5112-RKFCL datasheet(41/97 Pages) ATMEL

41 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

12.3.2. Master Input Slave Output (MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to

transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input

signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

12.3.3. SPI Serial Clock (SCK)

This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO

lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines.

12.3.4. Slave Select (SS)

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a

Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave

device by software through port pins (Figure 15). To prevent bus conflicts on the MISO line, only one slave should

be selected at a time by the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register

(SPSTA) to prevent multiple masters from driving MOSI and SCK (See Error conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general purpose if the following conditions are met:

The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration

can be found when only one Master is driving the network and there is no way that the SS pin will be

pulled low. Therefore, the MODF flag in the SPSTA will never be set1.

The Device is configured as a Slave with CPHA and SSDIS control bits set2. This kind of configuration

can happen when the system comprises one Master and one Slave only. Therefore, the device should always

be selected and there is no raison that the Master uses the SS pin to select the communicating Slave device.

12.3.5. Baud rate

In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the

SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of seven clock rates resulting from

the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock.

Table 21 gives the different clock rates selected by SPR2:SPR1:SPR0:

Table 21. SPI Master baud rate selection

Clearing SSDIS control bit does not clear MODF.

Special care should be taken not to set SSDIS control bit when CPHA = Õ0Õ because in this mode, the

SS is used to start the transmission.

SPR2:SPR1:SPR0

Clock Rate

Baud rate divisor (BD)

000

FCkIdle /2

001

FCkIdle /4

010

FCkIdle /8

011

FCkIdle/16

100

FCkIdle /32

101

FCkIdleH /64

110

FCkIdle /128

128

111

External clock

Output of BRG

T80C5112-RKFCL 数据表(PDF) 41 Page - ATMEL Corporation

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