T80C5112-RKFCL datasheet(20/97 Pages) ATMEL

20 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

8. Hardware Watchdog Timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The

WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default

disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,

SFR location 0A6H. When WDT is enabled, it will increment every machine cycle ( 6 internal clock periods) and

there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). The T0

bit of the WDTPRG register is used to select the overflow after 10 or 14 bits. When WDT overflows, it will

generate an internal reset. It will also drive an output RESET HIGH pulse at the emulator RST-pin.

If the crystal oscillator is selected with whe low speed option (32kHz), the low speed RC oscillator must not be

used. In this case the WDT will also use the low speed crystal oscillator.

8.1. Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When

WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.

The 14-bit counter overflows when it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device.

When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user

must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H

to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows,

it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC =

1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically

be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from

16ms to 2s @ FOSC = 12MHz and T0=0. To manage this feature, refer to WDTPRG register description, Table

8. (SFR0A7h).

Table 7. WDTRST Register

WDTRST Address (0A6h)

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

Reset value

T80C5112-RKFCL 数据表(PDF) 20 Page - ATMEL Corporation