数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

T80C5112-RKFCL 数据表(PDF) 42 Page - ATMEL Corporation

部件名 T80C5112-RKFCL
功能描述  8-bit Microcontroller with A/D converter
PDF  97 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

T80C5112-RKFCL 数据表(HTML) 42 Page - ATMEL Corporation

Back Button T80C5112-RKFCL Datasheet HTML 38Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 39Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 40Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 41Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 42Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 43Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 44Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 45Page - ATMEL Corporation T80C5112-RKFCL Datasheet HTML 46Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 42 / 97 page
background image
42
Rev. B - November 10, 2000
Preliminary
T80C5112
12.4. Functional Description
Figure 16 shows a detailed structure of the SPI module.
Figure 16. SPI Module Block Diagram
12.4.1. Operating Modes
The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Salve mode. The
configuration and initialization of the SPI module is made through one register:
·
The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
·
SPCON
·
The Serial Peripheral STAtus register (SPSTA)
·
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially).
A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A
Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending
data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in
synchronized with the same clock (Figure 17).
Shift Register
0
1
2
3
4
5
6
7
Internal Bus
Pin
Control
Logic
MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/2
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
IntClk
/32
/8
/16
Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA
SPR0
SPR1
CPOL
MSTR
SSDIS
SPEN
SPR2
SPCON
WCOL
MODF
SPIF
-
---
-
External Clk



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com