T80C5112-RKFCL datasheet(43/97 Pages) ATMEL

43 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Figure 17. Full-Duplex Master-Slave Interconnection

12.4.1.1. Master mode

The SPI operates in Master mode when the Master bit, MSTR1, in the SPCON register is set. Only one Master

SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to

the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to

the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously,

another byte shifts in from the Slave on the MasterÕs MISO pin. The transmission ends when the Serial Peripheral

transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from

the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral

Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT.

When the pin SS is pulled down during a transmission, the data is interrupted and when the transmission is

established again, the data present in the SPDAT is resent.

12.4.1.2. Slave mode

The SPI operates in Slave mode when the Master bit, MSTR2, in the SPCON register is cleared. Before a data

transmission occurs, the Slave Select pin, SS, of the Slave device must be set to Õ0Õ.SS must remain low until

the transmission is complete.

In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module.

After a byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the

SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another byte

enters the shift register3. A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle

before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data

already in the shift register from the previous transmission.

12.4.2. Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON:

the Clock POLarity (CPOL4) and the Clock PHAse (CPHA4). CPOL defines the default SCK line level in idle

state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are

sampled and the edges on which the output data are shifted (Figure 18 and Figure 19). The clock phase and polarity

should be identical for the Master SPI device and the communicating Slave device.

The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI.

The SPI module should be configured as a Slave before it is enabled (SPEN set).

The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.

Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = Õ0Õ).

8-bit Shift register

SPI

Clock Generator

Master MCU

8-bit Shift register

MISO

MOSI

SCK

VSS

VDD

Slave MCU

T80C5112-RKFCL 数据表(PDF) 43 Page - ATMEL Corporation

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