T80C5112-RKFCL datasheet(45/97 Pages) ATMEL

45 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

12.4.3. Error conditions

The following flags in the SPSTA signal SPI error conditions:

12.4.3.1. Mode Fault (MODF)

MODe Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with

the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control.

In this case, the SPI system is affected in the following ways:

An SPI receiver/error CPU interrupt request is generated.

The SPEN bit in SPCON is cleared. This disable the SPI.

The MSTR bit in SPCON is cleared.

When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes Õ0Õ.

However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there

is no way that another Master is attempting to drive the network. In this case, to prevent the MODF flag from

being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general

purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to

the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.

12.4.3.2. Write Collision (WCOL)

A Write COLlision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit

sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT.

12.4.3.3. Overrun Condition

An overrun condition occurs when the Master device tries to send several data bytes and the Slave devise has not

cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the

byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost.

This condition is not detected by the SPI peripheral.

12.4.4. Interrupts

Two SPI status flags can generate a CPU interrupt requests:

Table 22. SPI Interrupts

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF

bit generates transmitter CPU interrupt requests.

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode

of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests.

Figure 21 gives a logical view of the above statements:

Flag

Request

SPIF (SP data transfer)

SPI Transmitter Interrupt request

MODF (Mode Fault)

SPI Receiver/Error Interrupt Request (if SSDIS = Õ0Õ)

T80C5112-RKFCL 数据表(PDF) 45 Page - ATMEL Corporation

T80C5112-RKFCL 数据表(HTML) 45 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

数据表下载