T80C5112-RKFCL datasheet(61/97 Pages) ATMEL

61 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and

ADDL, it is cleared by software. If the bit EADC (IE1.1) is set, an interrupt occur when flag ADEOC is set (see

Figure 31). Clear this flag for re-arming the interrupt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection.

Before starting normal power reduction modes the ADC conversion has to be completed.

Table 34. Selected Analog input

14.5. Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage

equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line

linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range.

14.6. Clock Selection

The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in the AC characteristics

section. A prescaler is featured (ADCCLK) to generate the CONV_CK clock from the oscillator frequency.

Figure 30. A/D Converter clock

SCH2

SCH1

SCH0

Selected Analog input

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Prescaler ADCLK

A/D

Converter

CONV_CK

CKADC

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T80C5112-RKFCL 数据表(PDF) 61 Page - ATMEL Corporation

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