9/45

STLC5048

FUNCTIONAL DESCRIPTION (continued)

The needed TX gain can be set by proper programming of the GX block in combination with the TX amplifier.

Setting GTX=00h, the transmitted signal is muted and an idle PCM signal is generated on DX.

Concerning the CODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition,

via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits). In this case the signal sent

on the DX will take two adjacent PCM channels, proper care has to be taken in the time slot selection program-

ming (DXTS register).

The intrinsec non programmable gain GX0 set the TX path gain to 22.07dB. The absolute gain level (see elec-

trical characteristics) refers to this intrinsec gain.

RECEIVE PATH

The receive path of the STLC5048 consists of the decoder section, the gain block GR, the R filter, the channel

filters (LPR, HPR) the D/A converter and the output amplifier.

Concerning the DECODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition

via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits).

In this case the signal received on the DR input will take two adjacent PCM channels, proper care has to be

taken in the time slot selection programming (DRTS register).

The gain block GR is controlled by the GRX command allowing 30dB gain range in 0.01dB steps.

The R filter together the channel filters (LPR and HPR) performs the line equalization. The coefficients of the R

filter are programmed via the RFC command.

The signal is converted in the analog domain and amplified by the RX amplifier that can be programmed with

four different values (mute, 0dB, -6dB and -12dB) by means of RXG register.

Figure 3. Receive path.

VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent a DC current flow.

In order to get the best noise performances it is recommended to keep GRX value as close as possible to the

maximum (FFh) setting properly the additional attenuation by means of RXG.

The intrinsec non programmable gain GR0 set the RX path gain to -3.15dB. The absolute gain level (see elec-

trical characteristics) refers to this intrinsec gain.

PCM INTERFACE

The STLC5048 dedicates eight pins to the interface with the PCM highways.

MCLK represents the bit clock and is also used by the device as a source for the clock of the internal PLL.

Five possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels

PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating fre-

DR

RXG

VFRO

Σ∆

CONV.

GRO

A/

µ

GR

for RXG=0dB; GR=0dB

D00TL470