STLC5048

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EN2=0: Disable reception of selected time slot.

EN2=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO2 output.

R26..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred

to VFRO2 output.

If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most

significant bits in the programmed time slot, the 8 least significant bits in the following timeslot.

Example: if R26..R20=00:

Receive Time Slot ch #3 (DRTS3)

Addr=59h; Reset Value=00h

EN3=0: Disable reception of selected time slot.

EN3=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO3 output.

R36..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred

to VFRO3 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as

follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following

timeslot.

Example: if R36..R30=00:

PCMW Data Register (PCMWD)

Addr=5Ah; Reset Value=00h

Addr=5Bh; Reset Value=00h

This register is used to write receive PCM data via the MCU interface. Writing this register the IPCM interrupt

(if generated only by writing access) is automatically cleared.

In A/

µ law only the first 8 bit are used. In linear code option both registers must be used.

TS0

TS1

15

14

13

12

11

10

9865437210

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

1

011001

EN3

R36

R35

R34

R33

R32

R31

R30

TS0

TS1

15

14

13

12

11

10

9865437210

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

1

011010

D7

D6

D5

D4

D3

D2

D1

D0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

1

011011

D15

D14

D13

D12

D11

D10

D9

D8