STLC5048

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If bit 4 of CONF register (STA)=1 Static I/O mode:

CD0..3 are transferred to the corresponding CS pin if configured as static output (see register DATA1). For the

CS pins configured as static inputs the corresponding CD0..3 will be written by the values applied to those pins.

I/O Data Register channel #3 (DATA3)

Addr=08h; Reset Value=00h

Addr=09h; Reset Value=X0h

Used only if bit 4 of CONF register (STA)=0; Dynamic I/O mode:

When CS3 is active D311..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-

ister). For the I/O pins configured as inputs the corresponding D311..0 will be written by the values applied to

those pins while CS3 is low.

If bit4 of CONF register (STA) = 1

Static I/O mode:

Persistency Check Register (PCHK-A/B)

Addr=0Ah; Reset Value=00h

Addr=0Bh; Reset Value=00h

Two input signal per channel, labelled A and B, are submitted to persistency check.

In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the multiplexed lines IO0 (pin

13) and IO1 (pin 14).

In static mode (STA=1) persistency check is performed on four pairs of lines, assigned to each channel accord-

ing to the table:

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

000110

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

001000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

001001

CHAN #

Input A

Input B