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STLC5048 数据表(PDF) 18 Page - STMicroelectronics |
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STLC5048 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 45 page ![]() STLC5048 18/45 Interrupt Mask Register for I/O port (DMASK) Addr=11h; Reset Value=FFh Addr=12h; Reset Value=XFh MD11..0=1: The corresponding I/O doesn’t generate interrupt. MD11..0=0: The corresponding I/O (programmed as input) generate interrupt if a change of status is detected. Input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check register PCHKA/B. Line without persistency check generate an immedi- ate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt. Interrupt Mask Register for Interrupt (IMASK) Addr=13h; Reset Value=FFh For dynamic I/O configuration, MCn bits are the disable/enable interrupt related to the channel n. MC3..0=1: Any I/O line of the related channel #n is disabled to generate interrupt independently of DMASK setting. MC3..0=0: Any I/O line of the related channel #n is enabled to generate interrupt depending on DMASK setting. For static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are configured as I/O lines. MC0=1: The corresponding I/O cannot generate interrupt independently of DMASK setting. MC0=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DMASK setting. MC2=1: The corresponding I/O cannot generate interrupt independently of DATA3_L setting (bit 3..0). MC2=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DATA3_L setting (bit 3..0). MC3 and MC1 bit are not used in static mode. Input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check register PCHKA/B. Line without persistency check generate an immedi- ate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt MCF=1: The corresponding alarm bit (CKF) doesn’t generate interrupt. MCF=0: The corresponding alarm bit (CKF) can generate interrupt. MTV=1: The corresponding alarm bit (TV) doesn’t generate interrupt. MTV=0: The corresponding alarm bit (TV) can generate interrupt. MPCM =1 : The IPCM interrupt is masked (generation disabled). MPCM =0 : The IPCM interrupt is enabled (generation enabled). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W 0 010001 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W 0 010010 MD11 MD10 MD9 MD8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W 0 010011 x MTV MPCM MCF MC3 MC2 MC1 MC0 |
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