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STLC5048 数据表(PDF) 34 Page - STMicroelectronics |
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STLC5048 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 45 page ![]() STLC5048 34/45 Figure 4. SERIAL CONTROL PORT TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit fcclk Frequency of CCLK 8 MHz twch Period of CCLK High Measured from VIH to VIH 40 ns twcl Period of CCLK Low Measured from VIL to VIL 40 ns trc Rise time of CCLK Measured from VIL to VIH 20 ns tfc Fall time of CCLK Measured from VIH to VIL 20 ns thcs Hold time, CCLK low to CS low 10 ns thsc Hold time, CCLK low to CS high 10 ns tssc Setup time, CS transition to CCLK Low 10 ns tdsd Delay time, CS low to CO data valid 20 ns tcso CS off time 5 us tsdc Setup time, CI. Data in to CCLK low 10 ns thcd Hold time, CCLK low to CI invalid 10 ns tdcd Delay time, CCLK low to CO Data Out Valid 30 ns tddz Delay Time, CS or CCLK9 high to CO high impedance Pull up resistor = 1KOhm Cload = 30pF 30 ns MCLK FSX DX TSX DR D94TL157 THBF 123 456789 10 TRM TFM TWMH TWML 1 2 3 4 5 6 70 THBF 1 2 3 4 5 6 70 FSR TSDM THDM TSFB THBF TSFB THBF TDMD TDFD TDMT TDMT TZMT TZMT ELECTRICAL CHARACTERISTCS (continued) |
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