STLC5048

14/45

REGISTER DESCRIPTION

I/O Direction Register (DIR)

Addr=00h; Reset Value=00h

Addr=01h; Reset Value=X0h

IO11..0=0 I/O pin 11..0 is an input, data on the I/O input is written in DATAn register bit 11..0.

IO11..0=1 I/O pin 11..0 is an output, data contained in DATAn register bit 11..0 is transferred to the I/O output.

I/O Data Register channel #0 (DATA0)

Addr=02h; Reset Value=00h

Addr=03h; Reset Value=X0h

If bit 4 of CONF register (STA)=0 Dynamic I/O mode:

When CS0 is active D011..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-

ister). For the I/O pins configured as inputs the corresponding D011..0 will be written by the values applied to

those pins while CS0 is low.

If bit 4 of CONF register (STA)=1 Static I/O mode:

DS11..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins

configured as inputs the corresponding DS11..0 will be written by the values applied to those pins.

BIt7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

000000

BIt7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

000001

BIt7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

000010

BIt7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

000011

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

000010

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

0

000011