STLC5411FN datasheet(23/72 Pages) STMICROELECTRONICS

23 / 72 page

on Br is in the high impedance state.

A 24 ms timer is implemented in the UID. This

timer (when enabled) starts each time the sender

starts a byte sending and waits for a pre acknow-

ledgement.

C/I channel

The C/I channel is used for TXACT and RXACT

registers write and read operation. However, it is

possible to access to ACT registers by monitor

channel: this access is controled by the CID bit in

CR2 register.

The four bits code (C1,C2,C3,C4) of TXACT reg-

ister can be loaded in the UID by writing perma-

nently this code in the C/I channel time-slot on Bx

input every GCI frames. The UID takes into ac-

count the received code when it has been re-

ceived two consecutive times identical. When a

status change occurs in the RXACT register, the

new (C1,C2,C3,C4) code is sent in the C/I chan-

nel time-slot on Br output every GCI frames. This

E & A BITS TIMING

TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED

TWO BYTES MESSAGE - NORMAL TRANSMISSION

(M1)

XM1

1st byt e

pre-a ck

ac k

2n d byte

pr e-ac k

ack

3rd byt e??

pre- ack ??

EOM

Rea dy for

a new messag e

Ready

for a message

(M1)

(M2)

(X)

1st byt e

pre -ack

ac k

2nd by te

pre -ack

ab ort

EOM

1s t by te

pre -ack

3r d by te? ?

Read y for

retr ansmission

Rea dy fo r

a message

(M1)

(M2)

(X)

(or ab ort ack )

(M1)

XM1

Figure 5: GCI Monitor channel messaging examples.

STLC5411

23/72

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