STLC5411FN datasheet(25/72 Pages) STMICROELECTRONICS

25 / 72 page

the frame and superframe syncwords. STLC5411

is frame-synchronized when two consecutive

synchwords have been consecutively detected.

Frame lock will be maintained until six consecu-

tive errored sync-words are detected, which will

cause the flywheel to attempt to re-synchronize. If

a loss of frame sync condition persists for 480ms

the device will cease searching, cease transmit-

ting and go automatically into the RESET state,

ready for a further cold start. When UID is frame-

synchronized, it is superframe-locked upon the

first superframe sync-word detection. No loss of

superframe sync-word is provided.

While the receiver is synchronized, data is de-

scrambled using the specified polynomial, and in-

dividual channels demultiplexed and passed to

their respective processing circuits: user’s 2B+D

channel data is transmitted to the Digital Interface

through an elastic data buffer allowing any phase

deviation with the line; the activation/deactivation

bits (M4) are transmitted to the on-chip activation

sequencer; CRC is transmitted to CRC checking

section while maintenance data (eoc) and other

spare bits in the overhead channels (M4, M5, M6)

are stored in their respective Rx registers.

In NT applications, if the Digital Interface is se-

lected in master mode (see CR1) BCLK and FSa

clock outputs are phase-locked to the recovered

clock. If it is selected in Slave mode ie for NT1-2

application, the on-chip elastic buffers allow

BCLK and FSa to be input from an external

source, which must be frequency locked to the re-

ceived line signal ie using the SCLK output but

with arbitrary phase.

ELASTIC BUFFERS

The UID buffers the 2B+D data in elastic fifos

which are 3 line-frames deep in each direction.

When the Digital Interface is a timing slave, these

FIFOs compensate for relative jitter and wander

between the Digital Interface and the line. Each

buffer can absorb wander up to 18

µs at 80 KHz

max without ”slip”. This is particulary convenient

for NT1-2 or PABX application in case the local

reference clock is jitterized and wandered relative

to the incoming signal from the line.

MAINTENANCE FUNCTIONS

M channel

In each frame there are 6 ”overhead” bits assigned

to various control and maintenance functions.

Some programmable processing of these bits is

provided on chip while interaction with an external

controller provides the flexibility to take full advan-

tage of the maintenance channels. See OPR,

TXM4, TXM56, TXEOC, RXM4, RXM56, RXEOC

registers description fo details. New data written to

any of the Overhead bit Transmit Registers is

resynchronized internally to the next available

complete superframe or half superframe, as ap-

propriate.

Embedded Operation Channel (EOC)

The EOC channel consists of two complete 12

bits

messages

per

superframe,

distributed

through the M1, M2 and M3 bits of each frame.

Each message is composed of 3 fields; a 3 bit ad-

dress identifying the message destination/origin,

a 1 bit indicator for the data mode i.e. encoded

message or raw data, and an 8 bits information

field. The Control Interface (Microwire or Monitor

channel in GCI) provides access to the complete

12 bits of every message in TX and RX EOC reg-

isters.

When non-auto mode is selected, UID does not in-

terpret the received eoc messages e.g. ”send cor-

rupted CRC”; therefore the appropriate command

instruction must be written to the device e.g. ”set to

one bit CTC in register CR4”. It is possible to select

a transparent transmission mode in which the EOC

channel can be considered as a transparent 2 kbit/s

channel. See OPR register description for details.

When auto-mode is selected in GCI configuration,

UID performs automatic recognition / acknow-

ledgement of the EOC messages sent by the net-

work according to processing defined in ANSI

standard and illustrated in figure 9. When UID rec-

ognizes a message with the appropriate address

and a known command, it performs automatically

the relevant action inside the device and send a

message at the digital interface as appropriate. Ta-

ble 5 gives the list of recognized eoc messages and

associated actions.

When NT-RR-AUTO configuration is selected,

eoc addressing is processed according to appen-

dix E of T1E1.601 standard:

– If address of the eoc message received from

LT is in the range of 2 to 6, UID decrements

address and pass the message onto GCI.

– If address of the eoc message received from

GCI is in the range of 1 to 5, UID increments

address and pass the message onto the line

toward LT.

– If data/msg indicator is set to 0, UID pass

data on transparently with eoc address as de-

scribed above.

M4 channel

M4 bit positions of every frame is a channel in

which are transmitted data bits loaded from the

TXM4 transmit register and from the on-chip acti-

vation sequencer once the superframe. On the re-

ceive side, M4 bits from one complete superframe

are first validated and then stored in the RXM4

Receive Register or transmitted to on-chip activa-

tion sequencer. See OPR, TXM4 and RXM4 reg-

STLC5411

25/72

STLC5411FN 数据表(PDF) 25 Page - STMicroelectronics

STLC5411FN 数据表(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

数据表下载