STLC5411FN datasheet(26/72 Pages) STMICROELECTRONICS

26 / 72 page

isters description for details.

When NT1-AUTO or NT-RR-AUTO mode is se-

lected, bits ps1 and ps2 in M4 channel are con-

trolled directly by biasing input pins ES1 and ES2

respectively. e.g. ps1 is sent continuously to the

line equal 0 when ES1 input is forced at 0 Volt.

Spare M5 and M6 bits

The spare bit positions in the M5 and M6 field

form a channel in which are transmitted data bits

loaded from the TXM56 transmit register. On the

receive side, the spare bits in the M5 and M6

field are first validated and then stored in the

RXM56 receive register. See OPR, TXM56 and

RXM56 registers description for details.

CRC calculation/checking

In transmit direction, an on-chip CRC calculation

circuit automatically generates a checksum of the

2B+D+M4 bits using the specified 12th order

polynomial. Once per superframe, the CRC is

transmitted in the M5 and M6 bit positions. In re-

ceive direction, a checksum is again calculated

on the same bits as they are received and, at the

end of the superframe compared with the re-

ceived CRC. The result of this comparison gener-

ates a ”Far End Block Error” bit (febe) which is

transmitted back towards the other end of the

Line in the next but one superframe and an indi-

cation of Near End Block Error is sent to the sys-

tem by means of Register RXM56. If there is no

error in superframe, febe is set = 1, and if there is

one or more errors, febe is set = 0.

UID also includes two 8 bits Block Error Counters

associated with the febe bits transmitted and re-

ceived. It is then possible to select one Error

Counter per direction or to select only one counter

for both by means of bit C2E in OPR register. Block

error counting is always enabled but it is possible to

disabled the threshold interrupt and/or to en-

able/disable the interrupt issued at each received or

transmitted block error detection. See OPR register

for details.

Loopbacks

Six transparent or non transparent channel loop-

backs are provided by UID. It is therefore possible to

operate any loopback on B1, B2 and D channels line

to line or DSI/GCI to DSI/GCI. Command are

grouped in CR3 register.

In addition to the channel loopbacks in LT modes,

a complete transparent loopback operated at the

transmission side of UID allows the device to acti-

vate through an appropriate sequence with the

complete data stream looped-back to the re-

ceiver. Therefore, most of analog/digital clock and

data recovery circuits are tested. After activation

completed, an AI status indication is reported.

Complete loopback is enabled with ARL command

in TXACT register.

STLC5411

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STLC5411FN 数据表(PDF) 26 Page - STMicroelectronics

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