STLC5411FN datasheet(48/72 Pages) STMICROELECTRONICS

48 / 72 page

Receive M5 and M6 overhead bits register

(RXM56) (read only)

After reset: 1FH

m51r m61r m52r

febr

nebr

When the line is fully activated (super frame syn-

chronized), STLC5411 extracts the overhead bits.

When one of the received spare bits m51, m61,

m52 is validated following the criterias selected in

the Configuration Register OPR. The RXM56 reg-

ister content is queued in the interrupt register

stack, if no mask overhead bits is set (see MOB

bit in CR4 register). If the FIE bit in OPR register

is set high, the RXM56 register content is queued

in the interrupt register stack each time the febe

bit is received equal zero with bit feb equal 0.

The CRC received from the far-end is compared

at the end of the superframe with the CRC calcu-

lated by the UID during that superframe. If an er-

ror is detected, the febe bit in the transmit direc-

tion is forced equal zero in the next superframe. If

the CIE bit in the OPR register is set high, the

RXM56 register is queued in the interrupt register

stack at each CRC error detected with bit neb

equal zero. It is always possible to read this regis-

ter by writing RXM56 bit = 1 in RXOH register.

Activation control register (TXACT)

After reset: 0FH

C4C3C2C1

This register is constituted of four bits: (C1, C2,

C3, C4). In GCI mode, this register is normaly ad-

dressed by means of the C/I channel, but it is

possible to address it by means of the MONITOR

channel (see CID bit in CR2 register).

Activation indication register (RXACT)

(read only)

After reset: 0FH

C4r

C3r

C2r

C1r

This Register is constituted of four bits: (C1r, C2r,

C3r, C4r). At each activation status change,

RXACT is queued in the interrupt register stack.

In GCI mode, the C1-C4 bits are directly sent on

the C/I channel or monitor channel depending on

the CID bit in CR2 register. Activation Indication

instructions are coded on 4 bits according to acti-

vation control description. It is always possible to

read this register by writting RXACT bit = 1 in

RXOH register.

Block Error counter 1 (BEC1)

(read only)

After reset: 00H

ec7

ec6

ec5

ec4

ec3

ec2

ec1

ec0

This Register indicates the binary value of the

Block Error up-counter 1. Error are counted ac-

cording to C2E bit setting in register OPR (nebe +

febe or nebe only). When counter one reachs the

threshold ECT1, BEC1 register is queued in the

interrupt stack. BEC1 is reset to zero when it is

read.

Block Error counter 2 (BEC2)

(read only)

After reset: 00H

ec7

ec6

ec5

ec4

ec3

ec2

ec1

ec0

This Register indicates the binary value of the

Block Error up-counter 2. Febe errors are always

counted. According to C2E bit setting in register

OPR, when counter one reachs the threshold

ECT2, BEC2 register is queued in the interrupt

stack. BEC2 is reset to zero when it is read.

Threshold Block Error Counter 1 register

(ECT1)

After reset: FFH

ect17

ect16

ect15

ect14

ect13

ect12

ect11

It is possible to load in this register the binary

value of a threshold for the Block Error counter

1.When Block error counter reachs this value, an

Interrupt relative to BEC1 register is loaded in the

interrupt stack. This can be used as an early

alarm in case of degraded transmission.

Threshold Block Error Counter 2 register

(ECT2)

After reset: FFH

ect27

ect26

ect25

ect24

ect23

ect22

ect21

It is possible to load in this register the binary

value of a threshold for the Block Error counter

2.When Block error counter reachs this value, an

interrupt relative to BEC2 register is loaded in the

interrupt stack. This can be used as an early

alarm in case of degraded transmission.

Receive status register - read command

(RXOH) (Write only)

EOC

M56

ACT

STATUS

RST

Reset to zero of all the RXOH bits is automatic.

STLC5411

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