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数据搜索系统，热门电子元器件搜索 |
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STLC5466 数据表(PDF) 121 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 121 Page - STMicroelectronics |
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121 / 130 page  121/130 STLC5466 4.6 386EX: MOD0 = 0, MOD1 = 1, MOD2 = 0 Figure 4-11: 386EX read cycle (LBA# at Vdd) tx Parameter min max Unit ts Set up time/MCLK rising edge for CLKOUT, ALE, Addresses, WRNRD, NCS0/2 6ns th Hold time / MCLK rising edge for CLKOUT, WRNRD, NCS0/1/2 2 ns tdd Data out delay time / MCLK rising edge (50 pF) - 20 ns tdh Data out Hold time / MCLK rising edge (50 pF) 4 ns tdz Data floating delay / MCLK rising edge 4 15 ns ty Delay NRDY low / MCLK rising edge (50 pF) 4 20 ns tyz NRDY Delay floating / MCLK rising edge (50 pF) 4 10 ns MCLK NDS/NRD/ CLKOUT NAS/ ALE A1/23 A0/ NBLE SIZE1/ NBHE /NUDS 1) No wait state case R/W /NWR/ WRNRD NCS0/1/2 Dout 0/15 NDSACK0/ NDTACK/ NRDY 2) Wait state case R/W /NWR/ WRNRD NCS0/1/2 Dout 0/15 NDSACK0/ NDTACK/ NRDY cycle 1 cycle 2 ts th ts th ts th tdd ty ts ts th tdh tdz tyz n Twait td1 tdh tdz ty tyz |
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