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STM8AP5X2ATAY 数据表(PDF) 83 Page - STMicroelectronics |
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STM8AP5X2ATAY 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 100 page  STM8AF61xx, STM8AF51xx Electrical characteristics 83/100 11.3.10 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 35. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit fADC ADC clock frequency 2 MHz VDDA Analog supply 3 5.5 V VREF+ Positive reference voltage 2.75 VDDA V VREF- Negative reference voltage VSSA 0.5 V VAIN Conversion voltage range(1) 1. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. VSSA VDDA V Devices with external VREF+/ VREF- pins VREF- VREF+ V CADC Internal sample and hold capacitor 3pF tS (1) Sampling time (3 x 1/fADC) fADC = 2 MHz 1.5 µs tSTAB Wake-up time from standby 7 µs tCONV Total conversion time including sampling time (14 x 1/fADC) fADC = 2 MHz 7 µs |
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