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STM8AP5X2ATAY 数据表(PDF) 34 Page - STMicroelectronics |
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STM8AP5X2ATAY 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 100 page ![]() Interrupt table STM8AF61xx, STM8AF51xx 34/100 8 Interrupt table Table 8. STM8A interrupt table Priority Source block Description Interrupt vector address Wake-up from halt Comments - Reset Reset 6000h Yes Reset vector in ROM - TRAP SW interrupt 8004h 0TLI External top level interrupt 8008h 1AWU Auto wake up from halt 800Ch Yes 2 Clock controller Main clock controller 8010h 3 MISC Ext interrupt E0 8014h Yes Port A interrupts 4 MISC Ext interrupt E1 8018h Yes Port B interrupts 5 MISC Ext interrupt E2 801Ch Yes Port C interrupts 6 MISC Ext interrupt E3 8020h Yes Port D interrupts 7 MISC Ext interrupt E4 8024h Yes Port E interrupts 8 CAN CAN interrupt Rx 8028h Yes 9CAN CAN interrupt TX/ER/SC 802Ch 10 SPI End of transfer 8030h Yes 11 Timer 1 Update/overflow/ trigger/break 8034h 12 Timer 1 Capture/compare 8038h 13 Timer 2 Update/overflow/ break 803Ch Trigger not available on medium end timer 14 Timer 2 Capture/compare 8040h 15 Timer 3 Update/overflow/ break 8044h Trigger not available on medium end timer 16 Timer 3 Capture/compare 8048h 17 USART (SCI1) Tx complete/ ER/SPI EOT/SPI error 804Ch 18 USART (SCI1) Receive data full reg. 8050h 19 I2C I2C interrupts 8054h Yes 20 LINUART (SCI2) Tx complete/error/ SPI EOT/SPI error 8058h 21 LINUART (SCI2) Receive data full reg. 805Ch |
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