STM8AP5X2ATAY datasheet(15/100 Pages) STMICROELECTRONICS

15 / 100 page

STM8AF61xx, STM8AF51xx

Product overview

15/100

5.4.3

Read-out protection (ROP)

STM8A devices provide a read-out protection of the code and data memory by

programming the lock byte at address 4800h with the value AAh.

Read-out protection prevents reading and writing the program and data memory via the

debug module and SWIM interface. This protection is active in all device operation modes.

Any attempt to remove the protection by overwriting the lock byte triggers a global erase of

the program and data memory.

The ROP circuit may provide a temporary access for debugging or failure analysis. This is a

specific product option and must be specified while ordering STM8A products.

Temporary read access is protected by a user defined, 8-byte keyword that is different from

00h or FFh. The keys are stored in the option byte area.

Temporary read-out can be permanently disabled by means of the option byte TMU_DIS.

For enabling temporary read access the eight access keys have to be written in the TMU

registers. A wrong code does not change the protection status. More than eight

unsuccessful access trials trigger an erase of the program and data memory.

Entering the right key sequence enables a temporary read access to the code and data

memory after a delay of several milliseconds.

The procedure for temporary read access is as follows:

●

Activate SWIM mode under device reset - the CPU is stalled, code and data memory

are not visible by the debug module.

●

Enable the internal 128 KHz LSI oscillator

●

Write the 8eight key bytes into the TMU registers

●

Set the bit(0) of the TMU status register to 1. A dedicated state machine on an isolated

bus, compares the TMU register content with the key stored in the TMU option bytes.

During this periode read and write operations have no effect. A reset re-activates the

initial protection status. The comparison can be monitored by means of the TU_CTL_ST

●

In case of a successful key comparison, the SWIM interface enables read access to the

code and data memory and program execution. A comparison error does not change

the protection status but increments the counter MAXATT. If the counter content

exceedes eight unsuccessful trials, a global erase of the data and code memory is

triggered.

The read access is temporary. A device reset restores the initial protection.

5.4.4

Speed

●

Operation at up to 16 MHz CPU clock frequency without wait states. At a higher clock

frequency, a single wait state has to be inserted.

●

Programming time modes (same for word or block)

–

Fast programming: Without erase

–

Standard programming: Erase and program

STM8AP5X2ATAY 数据表(PDF) 15 Page - STMicroelectronics

STM8AP5X2ATAY 数据表(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载