STPCELITE datasheet(11/87 Pages) STMICROELECTRONICS

11 / 87 page

PIN DESCRIPTION

Release 1.3 - January 29, 2002

11/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

2. PIN DESCRIPTION

2.1. INTRODUCTION

The

STPC

Elite

integrates

most

the

functionalities of the PC architecture. As a result,

many of the traditional interconnections between

the host PC microprocessor and the peripheral

devices are totally internal to the STPC Elite. This

offers improved performance due to the tight

coupling

the

processor

core

and

these

peripherals. As a result many of the external pin

connections are made directly to the on-chip

peripheral functions.

Figure 2-1 shows the STPC Elite external

interfaces. It defines the main buses and their

function.

Table

2-1

describes

the

physical

implementation listing signals type and their

functionality. Table 2-2 provides a full pin listing

and description of pins. Table 2-7 provides a full

listing of pin locations of the STPC Elite package

by physical connection.

Note: Several interface pins are multiplexed with

other functions, refer to Table 2-4 and Table 2-5

for further details

Table 2-1. Signal Description

Group name

Qty

Basic Clocks reset & Xtal

Memory Interface

PCI interface

ISA

IDE

Local Bus

Grounds

VDD

Miscellaneous

GPIO

Unconnected

Total Pin Count

388

Figure 2-1. STPC Elite External Interfaces

SOUTH

NORTH

PCI

x86

SDRAM I/F

SYS

ISA/IDE/LB

STPC Elite

STPCELITE 数据表(PDF) 11 Page - STMicroelectronics

STPCELITE 数据表(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

数据表下载