STPCELITE datasheet(17/87 Pages) STMICROELECTRONICS

17 / 87 page

PIN DESCRIPTION

Release 1.3 - January 29, 2002

17/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

phase they carry the byte enable information.

These pins are inputs when a PCI master other

than the STPC Elite owns the bus and outputs

when the STPC Elite owns the bus.

FRAME#

Cycle Frame. This is the frame signal of

the PCI bus. It is an input when a PCI master owns

the bus and is an output when STPC Elite owns

the PCI bus.

IRDY# Initiator Ready. This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Elite initiates a bus cycle on the PCI

bus. It is used as an input during the PCI cycles

targeted to the STPC Elite to determine when the

current PCI master is ready to complete the

current transaction.

TRDY#

Target Ready. This is the target ready

signal of the PCI bus. It is driven as an output

when the STPC Elite is the target of the current

bus transaction. It is used as an input when STPC

Elite initiates a cycle on the PCI bus.

LOCK#

PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

DEVSEL# I/O Device Select. This signal is used

as an input when the STPC Elite initiates a bus

cycle on the PCI bus to determine if a PCI slave

device has decoded itself to be the target of the

current transaction. It is asserted as an output

either when the STPC Elite is the target of the

current PCI transaction or when no other device

asserts DEVSEL# prior to the subtractive decode

phase of the current PCI transaction.

STOP#

Stop Transaction. Stop is used to

implement the disconnect, retry and abort protocol

of the PCI bus. It is used as an input for the bus

cycles initiated by the STPC Elite and is used as

an output when a PCI master cycle is targeted to

the STPC Elite.

PAR

Parity Signal Transactions. This is the parity

signal of the PCI bus. This signal is used to

guarantee

even

parity

across

AD[31:0],

CBE#[3:0], and PAR. This signal is driven by the

master during the address phase and data phase

of write transactions. It is driven by the target

during data phase of read transactions. (Its

assertion is identical to that of the AD bus delayed

by one PCI clock cycle)

SERR#

System Error. This is the system error

signal of the PCI bus. It may, if enabled, be

asserted for one PCI clock cycle if target aborts a

STPC Elite initiated PCI transaction. Its assertion

by either the STPC Elite or by another PCI bus

agent will trigger the assertion of NMI to the host

CPU. This is an open drain output.

PCI_REQ#[2:0]

PCI Request. This pin are the

three external PCI master request pins. They

indicates to the PCI arbiter that the external

agents desire use of the bus.

PCI_GNT#[2:0]

PCI Grant. These pins indicate

that the PCI bus has been granted to the master

requesting it on its PCIREQ#.

PCI_INT[3:0] PCI Interrupt Request. These are

the PCI bus interrupt signals.

2.2.4. ISA INTERFACE

ISA_CLK, ISA_CLKX2 ISA Clock x1, x2. These

pins generate the Clock signal for the ISA bus and

a Doubled Clock signal. They are also used as the

multiplexer control lines for the Interrupt Controller

Interrupt input lines. ISA_CLK is generated from

either PCICLK/4 or OSC14M/ 2.

OSC14M

ISA bus synchronisation clock Output.

This is the buffered 14.318 MHz clock for the ISA

bus.

LA[23:17] Unlatched Address. When the ISA bus

is active, these pins are ISA Bus unlatched

address for 16-bit devices. When ISA bus is

accessed by any cycle initiated from PCI bus,

these pins are in output mode. When an ISA bus

master owns the bus, these pins are in input

mode.

SA[19:0]

ISA Address Bus. System address bus

of ISA on 8-bit slot. These pins are used as an

input when an ISA bus master owns the bus and

are outputs at all other times.

SD[15:0] I/O Data Bus. These pins are the

external databus to the ISA bus.

ALE Address Latch Enable. This is the address

latch enable output of the ISA bus and is asserted

by the STPC Elite to indicate that LA23-17, SA19-

0, AEN and SBHE# signals are valid. The ALE is

driven high during refresh, DMA master or an ISA

master cycles by the STPC Elite. ALE is driven

low after reset.

MEMR#

Memory Read. This is the memory read

command signal of the ISA bus. It is used as an

input when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

MEMW#

Memory Write. This is the memory write

command signal of the ISA bus. It is used as an

input when an ISA master owns the bus and is an

output at all other times.

SMEMR# System Memory Read. The STPC Elite

generates SMEMR# signal of the ISA bus only

STPCELITE 数据表(PDF) 17 Page - STMicroelectronics

STPCELITE 数据表(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

数据表下载