STPCELITE datasheet(38/87 Pages) STMICROELECTRONICS

38 / 87 page

ELECTRICAL SPECIFICATIONS

38/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

4.5.1. POWER ON SEQUENCE

Figure 4-3 describes the power-on sequence of

the STPC, also called cold reset.

There is no dependency between the different

power supplies and there is no constraint on their

rising time.

SYSRSTI# as no constraint on its rising edge but

must stay active until power supplies are all within

specifications,

margin

µs is even

recommended to let the STPC PLLs and strap

options stabilize.

Strap Options are continuously sampled during

SYSRSTI# low and must remain stable. Once

SYSRSTI# is high, they MUST NOT CHANGE

until SYSRSTO# goes high.

Bus activity starts only few clock cycles after the

release of SYSRSTO#. The toggling signals

depend on the STPC configuration.

In ISA mode, activity is visible on PCI prior to the

ISA bus as the controller is part of the south

bridge.

In Local Bus mode, the PCI bus is not accessed

and the Flash Chip Select is the control signal to

monitor.

Figure 4-3. Power-on timing diagram

S trap O ptions

Power Supplies

SYSRSTI#

SYSRSTO #

14 M H z

1.6 V

VALID CONFIG URATION

> 10 us

HCLK

PC I_C LK

2.3 m s

ISA C LK

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