STPCELITE datasheet(18/87 Pages) STMICROELECTRONICS

18 / 87 page

PIN DESCRIPTION

18/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

when the address is below one megabyte or the

cycle is a refresh cycle.

SMEMW# System Memory Write. The STPC Elite

generates SMEMW# signal of the ISA bus only

when the address is below one megabyte.

IOR# I/O Read. This is the IO read command

signal of the ISA bus. It is an input when an ISA

master owns the bus and is an output at all other

times.

IOW# I/O Write. This is the IO write command

signal of the ISA bus. It is an input when an ISA

master owns the bus and is an output at all other

times.

MCS16#

Memory Chip Select16. This is the

decode of LA23-17 address pins of the ISA

address bus without any qualification of the

command signal lines. MCS16# is always an

input. The STPC Elite ignores this signal during IO

and refresh cycles.

IOCS16#

IO Chip Select16. This signal is the

decode of SA15-0 address pins of the ISA

address bus without any qualification of the

command signals. The STPC Elite does not drive

IOCS16# (similar to PC-AT design). An ISA

master access to an internal register of the STPC

Elite is executed as an extended 8-bit IO cycle.

BHE#

System Bus High Enable. This signal, when

asserted, indicates that a data byte is being

transferred on SD15-8 lines. It is used as an input

when an ISA master owns the bus and is an

output at all other times.

ZWS#

Zero Wait State. This signal, when assert-

ed by addressed device, indicates that current cy-

cle can be shortened.

REF# Refresh Cycle. This is the refresh command

signal of the ISA bus. It is driven as an output

when the STPC Elite performs a refresh cycle on

the ISA bus. It is used as an input when an ISA

master owns the bus and is used to trigger a

refresh cycle.

The STPC Elite performs a pseudo hidden

refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

external

buffers.

The

host bus

then

relinquished while the refresh cycle continues on

the ISA bus.

MASTER#

Add On Card Owns Bus. This signal is

active when an ISA device has been granted bus

ownership.

AEN Address Enable. Address Enable is enabled

when the DMA controller is the bus owner to

indicate that a DMA transfer will occur. The

enabling of the signal indicates to IO devices to

ignore

the

IOR#/IOW#

signal

during

DMA

transfers.

IOCHCK# IO Channel Check. IO Channel Check

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal

becomes active upon seeing IOCHCK# active if

the corresponding bit in Port B is enabled.

IOCHRDY

Channel Ready. IOCHRDY is the IO

channel ready signal of the ISA bus and is driven

as an output in response to an ISA master cycle

targeted to the host bus or an internal register of

the STPC Elite. The STPC Elite monitors this

signal as an input when performing an ISA cycle

on behalf of the host CPU, DMA master or refresh.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Elite since

the access to the system memory can be

considerably delayed due UMA architecture.

ISAOE#

Bidirectional OE Control. This signal

controls the OE signal of the external transceiver

that connects the IDE DD bus and ISA SA bus.

GPIOCS# I/O General Purpose Chip Select. This

output signal is used by the external latch on ISA

bus to latch the data on the SD[7:0] bus. The latch

can be use by PMU unit to control the external

peripheral devices or any other desired function.

IRQ_MUX[3:0]

Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They

have to be encoded before connection to the

STPC Elite using ISACLK and ISACLKX2 as the

input selection strobes.

Note

that

IRQ8B,

which

convention

connected to the RTC, is inverted before being

sent to the interrupt controller, so that it may be

connected directly to the IRQ pin of the RTC.

DREQ_MUX[1:0] ISA Bus

Multiplexed DMA

Request. These are the ISA bus DMA request

signals.

They

are

encoded

before

connection to the STPC Elite using ISACLK and

ISACLKX2 as the input selection strobes.

DACK_ENC[2:0]

DMA Acknowledge. These are

the ISA bus DMA acknowledge signals. They are

encoded by the STPC Elite before output and

should be decoded externally using ISACLK and

ISACLKX2 as the control strobes.

ISA Terminal Count. This is the terminal count

output of the DMA controller and is connected to

the TC line of the ISA bus. It is asserted during the

last DMA transfer, when the byte count expires.

2.2.5. X-BUS INTERFACE PINS

RTCAS Real time clock address strobe. This

signal is asserted for any I/O write to port 70H.

STPCELITE 数据表(PDF) 18 Page - STMicroelectronics

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