STPCELITE datasheet(40/87 Pages) STMICROELECTRONICS

40 / 87 page

ELECTRICAL SPECIFICATIONS

40/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

4.5.3. SDRAM INTERFACE

Figure 4-5 and Table 4-8 list the AC characteris-

tics of the SDRAM interface. The MCLKx clocks

are the input clock of the SDRAM devices

The PC133 memory is recommended to reach

100MHz operation.

Figure 4-5. SDRAM Timing Diagram

MCLKI

STPC.output

STPC.input

MCLKx

Tdelay

Tsetup

Thold

Toutput (min)

Toutput (max)

Tcycle

Thigh

Tlow

Table 4-8. SDRAM Bus AC Timing

Name

Parameter

Min

Typ

Max

Unit

Tcycle

MCLKI Cycle Time

Thigh

MCLKI High Time

Tlow

MCLKI Low Time

MCLKI Rising Time

MCLKI Falling Time

Tdelay

MCLKx to MCLKI delay

-2

Toutput

MCLKI to Outputs Valid

5.2

8.7

MCLKI to DQM[ ] Outputs Valid

4.7

10.9

MCLKI to MD[ ] Outputs Valid

5.1

10.9

Tsetup

MD[63:0] setup to MCKLI without RDCLK

0.8

1.8

Thold

MD[63:0] hold from MCKLI without RDCLK

0.8

1.6

Note: These timing are for a load of 50pF.

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