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STPCELITE 数据表(PDF) 14 Page - STMicroelectronics

部件名 STPCELITE
功能描述  X86 Core General Purpose PC Compatible System - on - Chip
PDF  87 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPCELITE 数据表(HTML) 14 Page - STMicroelectronics

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PIN DESCRIPTION
14/87
Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
IDE CONTROL
DA[2:0]
O
BD8STRUP_FT
Address Bus
3
DD[15:12]
I/O
BD4STRP_FT
Data Bus
4
DD[11:0]
I/O
BD8STRUP_FT
Data Bus
12
PCS3#,PCS1#,SCS3#,SCS1#
O
BD8STRUP_FT
Primary & Secondary Chip Selects
4
DIORDY
O
BD8STRUP_FT
Data I/O Ready
1
PIRQ, SIRQ
I
BD4STRP_FT
Primary & Secondary Interrupt Request
2
PDRQ, SDRQ
I
BD4STRP_FT
Primary & Secondary DMA Request
2
PDACK#, SDACK#
O
BD8STRP_FT
Primary & Secondary DMA
Acknowledge
2
PDIOR#, SDIOR#
O
BD8STRUP_FT
Primary & Secondary I/O Channel Read
2
PDIOW#, SDIOW#
O
BD8STRP_FT
Primary & Secondary I/O Channel Write
2
MISCELLANEOUS
GPIO[15:0]
I/O
BD4STRP_FT
General Purpose I/Os
16
SPKRD
O
BD4STRP_FT
Speaker Device Output
1
SCL
I/O
BD4STRUP_FT
I²C Interface - Clock / Can be used for
VGA DDC[1] signal
1
SDA
I/O
BD4STRUP_FT
I²C Interface - Data / Can be used for
VGA DDC[0] signal
1
SCAN_ENABLE
I
TLCHTD_TC
Reserved (Test pin)
1
TCLK
I
BD4STRP_FT
Test clock
1
TDI
I
BD4STRP_FT
Test data input
1
TMS
I
BD4STRP_FT
Test mode input
1
TDO
O
BD4STRP_FT
Test data output
1
Table 2-2. Definition of Signal Pins
Signal Name
Dir
Buffer Type2
Description
Qty
Note1: These pins must be connected to the 2.5 V power supply. They must not be connected to the 3.3V supply.
Note2: See Table 2-3 for buffer type descriptions.



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