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STPCELITE 数据表(PDF) 31 Page - STMicroelectronics

部件名 STPCELITE
功能描述  X86 Core General Purpose PC Compatible System - on - Chip
PDF  87 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPCELITE 数据表(HTML) 31 Page - STMicroelectronics

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STRAP OPTION
Release 1.3 - January 29, 2002
31/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
3.1.4. HCLK STRAP REGISTER CONFIGURATION
HCLK_Strap
Access = 0022h/0023h
Regoffset = 05Fh
76543210
MD3
MD2
MD26
MD25
MD24
Rsv
This register defaults to the values sampled on MD[3:2] and MD[26:24] pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-3
MD[3:2] & [26:24]
These bits reflect the values sampled on MD[3:2] and MD[26:24] pins
respectively and control the Host clock frequency synthesizer, as given
in Table 3-4.
Bits 2-0
Rsv
Reserved
Table 3-4. HCLK Frequency
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
HCLK Frequency
00000
25 MHz
00001
50 MHz
00010
60 MHz
00011
66 MHz
01001
75 MHz
01110
82.5 MHz
10011
90 MHz
11001
100 MHz



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