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STPCELITE 数据表(PDF) 30 Page - STMicroelectronics |
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STPCELITE 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 87 page  STRAP OPTION 30/87 Release 1.3 - January 29, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 3.1.3. STRAP REGISTER 2 CONFIGURATION Strap2 Access = 0022h/0023h Regoffset = 04Ch 76543210 Rsv MD23 Rsv MD19 MD18 MD17 MD16 This register defaults to the values sampled on MD[23] and MD[19:16] pins after reset Bit Number Sampled Mnemonic Description Bits 7-6 Rsv Reserved Bit 5 MD23 Reserved Bit 4 Rsv Reserved Bit 3 MD19 Reserved Bit 2 MD18 Reserved Bit 1 MD17 This bit, programmed in parallel with MD[4], reflects the value sampled on MD[17] pin and controls the PCI clock output, as given in Table 3-3. Bit 0 MD16 Reserved Table 3-3. PCI Clock Output MD[4] MD[17] Description 0 X PCI clock output = HCLK / 4 1 0 PCI clock output = HCLK / 3 1 1 PCI clock output = HCLK / 2 |
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